Results 1  10
of
65
Reconfigurable Computing Systems
 Proceedings of the IEEE
, 2002
"... Reconfigurable computing is emerging as the new paradigm for satisfying the simultaneous demand for application performance and flexibility. The ability to customize the architecture to match the computation and the dataflow of the application has demonstrated significant performance benefits compar ..."
Abstract

Cited by 50 (0 self)
 Add to MetaCart
Reconfigurable computing is emerging as the new paradigm for satisfying the simultaneous demand for application performance and flexibility. The ability to customize the architecture to match the computation and the dataflow of the application has demonstrated significant performance benefits compared to general purpose architectures. Computer vision applications are one class of applications that have significant heterogeneity in their computation and communication structures. At the low level vision algorithms have regular, repetitive computations operating on large sets of image data with predictable data dependencies. At the higher level the computations have irregular dependencies. Computer vision application characteristics have significant overlap with the advantages of reconfigurable architectures. The main focus of the paper is on outlining the methodologies required to realize the potential of reconfigurable architectures for vision applications. After giving a broad introduction to reconfigurable computing, the advantages of utilizing reconfigurable architectures for vision applications are outlined and illustrated using example computations. The paper discusses the development of fundamental configurable computing models that abstract the underlying hardware for high level application mapping. The Hybrid System Architecture Model and algorithms utilizing the model are illustrated to demonstrate a formal framework. The paper also outlines ongoing research and provides a comprehensive list of references for further reading.
The Complexity of Reconfiguring Network Models
, 1992
"... This paper concerns some of the theoretical complexity aspects of the reconfigurable network model. The computational power of the model is investigated under several variants, depending on the type of switches (or switch operations) assumed by the network nodes. Computational power is evaluated by ..."
Abstract

Cited by 19 (5 self)
 Add to MetaCart
This paper concerns some of the theoretical complexity aspects of the reconfigurable network model. The computational power of the model is investigated under several variants, depending on the type of switches (or switch operations) assumed by the network nodes. Computational power is evaluated by focusing on the set of problems computable in constant time in each variant. A hierarchy of such problem classes corresponding to different variants is shown to exist and is placed relative to traditional classes of complexity theory. Department of Mathematics and Computer Science, The Haifa University, Haifa, Israel. Email: yosi@mathcs2.haifa.ac.il y Department of Computer Science, Technische Universitat Munchen, 80290 Munchen, Germany. Email: lange@informatik.tumuenchen.de z Department of Applied Mathematics and Computer Science, The Weizmann Institute, Rehovot 76100, Israel. Email: peleg@wisdom.weizmann.ac.il. Supported in part by an Allon Fellowship, by a Bantrell Fellowship an...
Selection on the reconfigurable mesh
 Proceedings of 4th Symposium on the Frontiers of Massively Parallel Computation
, 1992
"... ..."
Routing and Sorting on Meshes with Row and Column Buses
, 1994
"... of the 27th Annual IEEE Symposium on Foundations of Computer Science, pages 264273, 1986. [50] T. Suel. Routing and sorting on meshes with row and column buses. In Proceedings of the 8th International Parallel Processing Symposium, April 1994. [51] B. Wang and G. Chen. Constant time algorithms fo ..."
Abstract

Cited by 13 (1 self)
 Add to MetaCart
of the 27th Annual IEEE Symposium on Foundations of Computer Science, pages 264273, 1986. [50] T. Suel. Routing and sorting on meshes with row and column buses. In Proceedings of the 8th International Parallel Processing Symposium, April 1994. [51] B. Wang and G. Chen. Constant time algorithms for the transitive closure and some related graph problems on processor arrays with reconfigurable bus systems. IEEE Transactions on Parallel and Distributed Systems, 1:500507, 1990. [27] M. Kunde. Block gossiping on grids and tori: Deterministic sorting and routing match the bisection bound. In Proceedings of the 1st Annual European Symposium on Algorithms, September 1993. [28] R. E. Ladner, J. Lampe, and R. Rogers. Vector prefix addition on subbus mesh computers. In Proceedings of the 5th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 387396, June 1993. [29] F. T. Leighton. Tight bounds on the com
A Novel Deterministic Sampling Scheme with Applications to BroadcastEfficient Sorting on the Reconfigurable Mesh
 Journal of Parallel and Distributed Computing
, 1996
"... The main contribution of this work is to present a simple deterministic sampling strategy that, when used for bucket sorting, yields buckets that are remarkably well balanced, making costly balancing unnecessary. To the best of our knowledge this is the first instance of a deterministic sampling ..."
Abstract

Cited by 13 (3 self)
 Add to MetaCart
The main contribution of this work is to present a simple deterministic sampling strategy that, when used for bucket sorting, yields buckets that are remarkably well balanced, making costly balancing unnecessary. To the best of our knowledge this is the first instance of a deterministic sampling strategy featuring this performance. Although the strategy is perfectly general, we illustrate its power by devising a VLSIoptimal, O(1) time sorting algorithm for the reconfigurable mesh. As a byproduct of the inherent simplicity of our sampling and bucketing scheme we show that our sorting algorithm can be implemented using only 35 broadcast operations, a substantial improvement over the previously best known algorithm that requires 59 broadcasts. Keywords: deterministic sampling, bucket sort, reconfigurable meshes, sorting, VLSI optimal algorithms, constanttime algorithms 1 Introduction Sorting is, unquestionably, one of the fundamental operations in computer science. A natura...
Multicast Virtual Topologies for Collective Communication in MPCs and ATM Clusters
 IN PROCEEDINGS OF THE SUPERCOMPUTING
, 1995
"... This paper defines and describes the properties of a multicast virtual topology, the Marray, and a resourceefficient variation, the REMarray. It is shown how several collective operations can be implemented efficiently using these virtual topologies, while maintaining low complexity. Because the ..."
Abstract

Cited by 10 (3 self)
 Add to MetaCart
This paper defines and describes the properties of a multicast virtual topology, the Marray, and a resourceefficient variation, the REMarray. It is shown how several collective operations can be implemented efficiently using these virtual topologies, while maintaining low complexity. Because the methods are applicable to any parallel computing environment that supports multicast communication in hardware, they provide a framework for collective communication libraries that are portable and yet take advantage of such lowlevel hardware functionality. In particular, the paper describes the practical issues of using these methods in wormholerouted massively parallel computers (MPCs) and in workstation clusters connected by Asynchronous Transfer Mode (ATM) networks. Performance results are given for both environments.
Reconfigurable Meshes: Theory and Practice
 In Reconfigurable Architectures Workshop, RAW'97
, 1997
"... Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computi ..."
Abstract

Cited by 10 (6 self)
 Add to MetaCart
Configurable computing has recently gained much attention with the promise of delivering an order of magnitude performance improvement over general purpose processors. In this paper we contrast the abstract models of reconfigurable architectures and actual hardware available for configurable computing systems. There is a wealth of ideas related to abstract models of reconfigurable architectures and fast parallel algorithms which exploit the reconfiguration potential in nontrivial ways. We summarize these abstract models and illustrate the power of these models using several example algorithms. We identify the practical problems in implementing these models in VLSI and describe some prototype implementations. Commercial FPGA devices which are being touted as the solution for building configurable computing systems are also examined. The MAARC 2 project at USC endeavors to bridge this gap between the abstract and the real worlds. 1 This work was supported by DARPA under contract DABT...
Communicationefficient sorting algorithms on reconfigurable array of processors with slotted optical buses
 Slotted Optical Buses,ยบ J. Parallel and Distributed Computing
, 1999
"... The reconfigurable array with slotted optical buses (RASOB) has recently received a lot of attention from the research community. In this paper, we first discuss the reconfiguration methods and communication capabilities of the RASOB architecture. Then, we use this architecture for the implementatio ..."
Abstract

Cited by 7 (1 self)
 Add to MetaCart
The reconfigurable array with slotted optical buses (RASOB) has recently received a lot of attention from the research community. In this paper, we first discuss the reconfiguration methods and communication capabilities of the RASOB architecture. Then, we use this architecture for the implementation of efficient sorting algorithms on the 1D RASOB and the 2D RASOB. Our parallel sorting algorithm on the 1D RASOB is based on an efficient divideandconquer scheme. It sorts N data items using N processors in O(k) communication cycles where k is the size of the data items to be sorted in bits. We further develop a parallel sorting algorithm on the 2D RASOB based on the sorting algorithm on the 1D RASOB in conjunction with the well known Rotatesort algorithm. Similarly, this algorithm sorts N data items on a 2D RASOB of size N in O(k) communication cycles. These sorting algorithms are much more efficient than stateoftheart sorting algorithms on reconfigurable arrays of processors with electronic buses using the same
Optimal average case sorting on arrays
 Proceedings of the 12th Symposium on Theoretical Aspects of Computer Science, number 900 in Lecture Notes in Computer Science
, 1995
"... Abstract. We present algorithms for sorting and routing on twodimensional meshconnected parallel architectures that are optimal on average. If one processor has many packets then we asymptotically halve the up to now best running times. For a load of one optimal algorithms are known for the mesh. ..."
Abstract

Cited by 7 (2 self)
 Add to MetaCart
Abstract. We present algorithms for sorting and routing on twodimensional meshconnected parallel architectures that are optimal on average. If one processor has many packets then we asymptotically halve the up to now best running times. For a load of one optimal algorithms are known for the mesh. We improve this to a load of eight without increasing the running time. For tori no optimal algorithms were known even for a load of one. Our algorithm is optimal for every load. Other architectures we consider include meshes with diagonals and reconfigurable meshes. Furthermore, the method applies to meshes of arbitrary higher dimensions and also enables optimal solutions for the routing problem. 1 Introduction We present deterministic algorithms that sort and route on meshconnected computers fast on average. For important, fundamental classes of problems (so called hh relations) we completely solve the problem in that sense that our approach is optimal for all cases. (We present matching lower bounds.) A twodimensional meshconnected computer is a processor array, where each processor has one bidirectional connection to each of its four neighbors. Meshes are a promising parallel architecture due to their scalability, their regular interconnection structure with its locality of communication, and since they need only linear space in the VLSImodel. We also consider meshes with wraparound connections, also known as tori, meshes with additional diagonal connections, and reconfigurable meshes.
Constant Time Algorithms for Computing the Contour of Maximal Elements on a Reconfigurable Mesh
"... There has recently been an interest in the introduction of reconfigurable buses to existing parallel architectures. Among them the Reconfigurable Mesh (RM) draws much attention because of its simplicity. This paper presents three constant time algorithms to compute the contour of the maximal element ..."
Abstract

Cited by 7 (4 self)
 Add to MetaCart
There has recently been an interest in the introduction of reconfigurable buses to existing parallel architectures. Among them the Reconfigurable Mesh (RM) draws much attention because of its simplicity. This paper presents three constant time algorithms to compute the contour of the maximal elements of N planar points on the RM. The first algorithm employs an RM of size N \ThetaN while the second one uses a 3D RM of size p N \Theta p N \Theta p N . We further extend the result to kD RM of size N 1=(k\Gamma1) \Theta N 1=(k\Gamma1) \Theta \Delta \Delta \Delta \Theta N 1=(k\Gamma1) . Keywords: Reconfigurable mesh; Parallel algorithm; Computational geometry 1 Introduction It is well known that interprocessor communications and simultaneous memory accesses often act as bottlenecks in presentday parallel machines [1]. Bus systems have been introduced recently to a number of parallel machines to address this problem. Examples include the Bus Automaton [2], the Reconfigurable ...