Abstract — This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers, as well as the improved metrics relating to the coverage of assertion checkers. The proposed techniques have been successfully incorporated into the MBAC checker generator. I.

Symbolic debuggers are system development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the source level. In response to a user query, the debugger must be able to retrieve and display the value of a source variable in a manner consistent with what the user expects with respect to the source statement where execution has halted. However, when a behavioral specification has been optimized using transformations, values of variables may either be inaccessible in the run-time state or inconsistent with what the user expects. In this paper, we address the problem that pertains to the retrieval of source values for globally optimized behavioral specifications. We have developed a set of techniques that, given a behavioral specification CDFG, enforce computation of a selected subset Vcut of user variables such that (i) all other variables v 2 CDFG can be computed from Vcut and (ii) this enforcement has min...

LOGICAL HARDWARE DEBUGGERS FOR FPGA-BASED SYSTEMS Paul S. Graham Electrical and Computer Engineering Doctor of Philosophy Designers using Field Programmable Gate Arrays (FPGAs) have generally performed hardware debugging and verification for FPGA designs much like they would for other digital hardware designs, using simulation and external test equipment. Due to common SRAM-based FPGA device features such as JTAG interfaces, configuration readback, and reprogrammability, the debugging process for FPGA designs can resemble common software debugging approaches where designs are debugged by executing directly on the target hardware system using debuggers which provide high levels of design observability, controllability, execution control, and interactivity while presenting high-level, logical views of the designs. This dissertation demonstrates that such a hardware debugging system is possible for FPGA-based designs by developing such a system for FPGA-based custom computing machines (FCCMs) using the JHDL design environment and other tools such as JBits and JRoute. This dissertation also demonstrates the use of FPGA configuration readback for providing FPGA design observability support for hardware debuggers as well as the use of design modification or instrumentation to improve design observability, controllability, and execution control. The most notable of these design instrumentation or modification techniques are: design-level scan, which provides complete design observability and controllability; bitstream-modifiable embedded logic analyzers, which provide quickly configurable, localized observability; and bitstream modification for the interactive controllability of an FPGA design's state.