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Structuring and Automating Hardware Proofs in a HigherOrder TheoremProving Environment
 Formal Methods in System Design
, 1993
"... . In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically design ..."
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. In this article we present a structured approach to formal hardware verification by modelling circuits at the registertransfer level using a restricted form of higherorder logic. This restricted form of higherorder logic is sufficient for obtaining succinct descriptions of hierarchically designed registertransfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardwarespecific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a generalpurpose, firstorder prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higherorder logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...
Formal Hardware Verification By Symbolic Trajectory Evaluation
, 1997
"... Formal verification uses a set of languages, tools, and techniques to mathematically reason about the correctness of a hardware system. The form of mathematical reasoning is dependent upon the hardware system. This thesis concentrates on hardware systems that have a simple deterministic highlevel s ..."
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Cited by 19 (1 self)
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Formal verification uses a set of languages, tools, and techniques to mathematically reason about the correctness of a hardware system. The form of mathematical reasoning is dependent upon the hardware system. This thesis concentrates on hardware systems that have a simple deterministic highlevel specification but have implementations that exhibit highly nondeterministic behaviors. A typical example of such hardware systems are processors. At the high level, the sequencing model inherent in processors is the sequential execution model. The underlying implementation, however, uses features such as nondeterministic interface protocols, instruction pipelines, and multiple instruction issue which leads to nondeterministic behaviors. The goal is to develop a methodology with which a designer can show that a circuit fulfills the abstract specification of the desired system behavior. The abstract specification describes the highlevel behavior of the system independent of any timing or implem...
An Example of Interactive Hardware Transformation
, 1993
"... This article presents an example of correct circuit design through interactive transformation. Interactive transformation differs from traditional hardware design transformation frameworks in that it focuses on the issue of finding suitable hardware architecture for the specified system and the issu ..."
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Cited by 10 (1 self)
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This article presents an example of correct circuit design through interactive transformation. Interactive transformation differs from traditional hardware design transformation frameworks in that it focuses on the issue of finding suitable hardware architecture for the specified system and the issue of architecture correctness. The transformation framework divides every transformation in designs into two steps. The first step is to find a proper architecture implementation. Although the framework does not guarantee existence of such an implementation, nor its discovery, it does provide a characterization of architectural implementation so that the question "is this a correct implementation?" can be answered by equational rewriting. The framework allows a correct architecture implementation to be automatically incorporated with control descriptions to obtain a new system description. The significance of this transformation framework lies in the fact that it requires simpler mechanism o...
A Practical Methodology for the Formal Verification of RISC Processors
, 1995
"... In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage leve ..."
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In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage level, the clock phase level and the hardware implementation. The use of this model allows us to successively prove the correctness between two neighbouring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into two independent steps. The first step shows that each architectural instruction is implemented correctly by the sequential execution of its pipeline stages. The second step shows that the instructions are correctly processed by the pipeline in that we prove that under certain constraints from the actual architecture, no conflic...
Computer Assisted Analysis Of Multiprocessor Memory Systems
, 1996
"... Parallel architecture becomes more and more attractive as the demand for performance increases. One of the most important classes of parallel machines is that of shared memory architectures, which are perceived as easier to program than other parallel architectures. In a shared memory multiprocessor ..."
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Cited by 7 (1 self)
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Parallel architecture becomes more and more attractive as the demand for performance increases. One of the most important classes of parallel machines is that of shared memory architectures, which are perceived as easier to program than other parallel architectures. In a shared memory multiprocessor architecture, a memory model describes the behavior of the memory system as observed at the userlevel. A cache coherence protocol aims to conform to a memory model by maintaining consistency among the multiple copies of cached data and the data in main memory. Memory models and cache coherence protocols can be quite complex and subtle, creating a real possibility of misunderstandings and actual design errors. In this thesis, we will present solutions to the problems of specifying memory models and verifying the correctness of cache coherence protocols. Weaker memory models for multiprocessor systems allow higherperformance implementation techniques for memory systems. However, weak memor...
Hardware Design Based on Verilog HDL
, 1998
"... Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to ..."
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Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verification. This thesis proposes a unified approach to hardware design in which both simulation and formal verification can coexist. Relational Duration Calculus (an extension of Duration Calculus) is developed and used to define the formal semantics of Verilog HDL (a standard industry hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hardware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog programs, formal verification and the use of algebraic laws during the design stage.
Structuring Hardware Proofs: First steps towards Automation in HigherOrder Environment
 Proc. VLSI '91
, 1991
"... Most proofs of hardware in an higherorder logic environment follow a definite pattern.##tte observation is used to give a methodology for hardware proofs in order to isolate the## 487594 where the designer's creativity is required, and to automate the remaining tedious##diou tasks. The interactive ..."
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Cited by 4 (3 self)
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Most proofs of hardware in an higherorder logic environment follow a definite pattern.##tte observation is used to give a methodology for hardware proofs in order to isolate the## 487594 where the designer's creativity is required, and to automate the remaining tedious##diou tasks. The interactive HOL theorem prover has been extended by generalized hardware specific ##ecific for simplifying proofs and an automatic theorem prover, called FAUST,##US proving the simplified subgoals. 1. INTRODUCTION Although formal verification of hardware has been the focus of extensive research in the##e 504 past [13], it has not yet been embedded within the toolkit of normal##rmal 4 designers. The main reasons for this are twofold  the existing automatic approaches can handle only a limited class of circuits, and the powerful interactive approaches can be driven##ive by logicians. In this paper we present a method for structuring hardware proofs within an##47764279 environment, thus isolating the...
A Method for Approximate Equivalence Checking
 in Proceedings of the 30th IEEE International Symposium on MultipleValued Logic, Portland OR
, 2000
"... An approximate equivalence checking method is developed based on the use of partial Haar spectral diagrams (HSDs). Partial HSDs are defined and used to represent a subset of the Haar spectral coefficients for two functions. Due to the uniqueness properties of the Haar transform, a necessary conditio ..."
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Cited by 3 (1 self)
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An approximate equivalence checking method is developed based on the use of partial Haar spectral diagrams (HSDs). Partial HSDs are defined and used to represent a subset of the Haar spectral coefficients for two functions. Due to the uniqueness properties of the Haar transform, a necessary condition for equivalence is that the individual coefficients must have the same value. The probability that two functions are equivalent is then computed based on the number of observed, samevalued, Haar coefficients. The method described here can be useful for the case where two candidate functions require extreme amounts of computational resources for exact equivalence checking. For simplicity, the technique is explained for the binary case first and extensions to Multiple Valued Logic (MVL) are shown afterwards. Experimental results are provided to validate the effectiveness of this approach. 1. Introduction The equivalence checking problem for two logic functions of n variables, f(X) and g(Y...
Rapid Prototyping of Microelectronic Systems
 Advances in Computers
, 1995
"... The need for reduced time to market of new designs has mandated the development of a new generation of computeraided design tools and design methodologies. The active pursuit of a substantial time reduction in the design process is encompassed in rapid system prototyping. This chapter introduces th ..."
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The need for reduced time to market of new designs has mandated the development of a new generation of computeraided design tools and design methodologies. The active pursuit of a substantial time reduction in the design process is encompassed in rapid system prototyping. This chapter introduces the field and the disciplines it comprises, and presents extensive examples of research activities in many key disciplines. New technologies, such as field programmable gate arrays, and new methodologies, such as subsystem reusability, are presented. The directions in formalizing the process of system design from specifications through delivery of a functional system are also discussed. Advances in Computers, V. 40, M. V. Zelkowitz (ed.), Academic Press, In Press, 1995 Contents 1 Introduction 4 2 What Is RSP? 5 2.1 Elements of RSP : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 2.1.1 System Specifications, Verification, and Reusability : : : : : : ...
Le Algebre Evolventi per la validazione di hardware
, 1996
"... nico, per cui nasce l'esigenza di testare i prodotti prima di commercializzarli, ossia di provarne in maniera rigorosa la correttezza. Questa prova in verit`a non `e per niente banale, anzi attualmente non esiste una metodologia generale, sicura e a costi ragionevoli [Bel95]. Gli stimoli a continua ..."
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nico, per cui nasce l'esigenza di testare i prodotti prima di commercializzarli, ossia di provarne in maniera rigorosa la correttezza. Questa prova in verit`a non `e per niente banale, anzi attualmente non esiste una metodologia generale, sicura e a costi ragionevoli [Bel95]. Gli stimoli a continuare la ricerca in questa direzione sono molto forti: basti pensare alle grosse cifre perse dalla Intel col suo ultimo prodotto, il pentium, che ha rivelato degli errori solo dopo la commercializzazione. L'articolo `e organizzato come segue: la sezione 2 affronta il concetto di validazione di dispositivi elettronici, presentando le metodologie attualmente conosciute  simulazione e verifica formale , con un'accurata formalizzazione della seconda, l'unica che pu`o portare ad una dimostrazione matematica della 1 correttezza. Essa contiene anche una breve descrizione del formalismo