Domain-specific languages (DSLs) are languages tailored to a specific application domain.

This paper describes a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptography (PKC), i.e., Elliptic Curve (EC) and RSA Cryptosystems. The processor consists of special operational blocks for Montgomery Modular Multiplication, modular addition/substraction, EC Point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

Distributedsynchronizationforparallelsimulationisgenerallyclassifiedasbeingeitheroptimisticorconservative. Whileconsiderableinvestigationshavebeenconducted toanalyzeandoptimizeeachofthesesynchronization strategies,verylittlestudyonthedefinitionandstrictness ofcausalityhavebeenconducted.Dowereallyneed topreservecausalityinalltypesofsimulations?This paperattemptstoanswerthisquestion.Wearguethat significantperformancegainscanbemadebyreconsideringthisdefinitiontodecideiftheparallelsimulation needstopreservecausality.Weinvestigatethefeasibility ofunsynchronizedparallelsimulationthroughtheuseof severalqueuingmodelsimulationsandpresentacomparativeanalysisbetweenunsynchronizedandTimeWarp simulation.

This report studies the continuous time and mixed-signal simulation techniques in the Ptolemy II environment. Unlike the nodal analysis representation usually seen in circuit simulators, the continuous time systems are modeled as signal-flow block diagrams in Ptolemy II. This representation is suitable for system-level specification, and the interaction semantics with other models of computation can be easily studied and implemented. The numerical solving methods for ordinary differential equations are discussed from the tagged-signal point of view and implemented in the continuous time domain. The breakpoint handling techniques are essential for performing correct simulation and supporting the interaction with other domains. Mixed-signal simulation of continuous time and discrete event models is discussed. Event detection can be performed using the breakpoint handling mechanism. The coordination of the execution of the two models are discussed. The result shows that when a continuous subsystem is embedded in a discrete event system, the inner system must run ahead of the global time and be able to roll back. Based on the result, a correct and efficient simulation strategy is presented. As a case study, the mixed-signal simulation techniques are applied to a micro accelerometer with sigma-delta kind of digital feedback.

Modular decomposition and functional abstraction are commonly employed to accommodate the growing size and complexity of modern designs. In the test domain, a divide & conquer type of approach is utilized, wherein test is locally generated at each module's boundary and consequently translated to global design test. We present an RTL analysis methodology that identifies the test justification and propagation bottlenecks, facilitating a judicious DFT insertion process. We introduce two mechanisms for capturing, without reasoning on the complete functional space, data and control module behavior related to test translation. A traversal algorithm that identifies the test translation bottlenecks in the design is described. The algorithm is capable of handling cyclic behavior, reconvergence and variable bit-widths in an efficient manner. We demonstrate our scheme on representative examples, unveiling its potential of accurately identifying and consequently minimizing the reported controlla...

P systems are massively parallel systems. Software simulations do no usually allow to exploit this parallelism. We present a parallel hardware implementation of a special class of membrane systems. The implementation is based on a universal membrane hardware component that allows to eciently run membrane systems on specialized hardware such as FPGAs. The implementation is presented in detail as well as performance results and an example.

The MATRIX (Multipurpose Array of Tactile Rods for Interactive eXpression) is a new musical interface for amateurs and professionals alike. It gives users a 3dimensional tangible interface to control music using their hands, and can be used in conjunction with a traditional musical instrument and a microphone, or as a stand-alone gestural input device. The surface of the MATRIX acts as a real-time interface that can manipulate the parameters of a synthesis engine or effect algorithm in response to a performer's expressive gestures. One example is to have the rods of the MATRIX control the individual grains of a granular synthesizer, thereby "sonically sculpting" the microstructure of a sound. In this way, the MATRIX provides an intuitive method of manipulating sound with a very high level of real-time control.

Chip fabrication technology continues to plunge deeper into submicron levels requiring hardware designers to utilize everincreasing amounts of logic and shorten design time. Toward that end, high-level languages such as C/C++ are becoming popular for hardware description and synthesis in order to more quickly leverage complex algorithms. Similarly, as logic density increases due to technology, power dissipation becomes a progressively more important metric of hardware design. PACT HDL, a C to HDL compiler, merges automated hardware synthesis of high-level algorithms with power and performance optimizations and targets arbitrary hardware architectures, particularly in a System on a Chip (SoC) setting that incorporates reprogrammable and application-specific hardware. PACT HDL is intended for applications well suited to custom hardware implementation such as image and signal processing codes. By making the compiler modular and flexible, optimizations may be executed in any order and at different levels in the compilation process. PACT HDL generates industry standard HDL codes, such as RTL Verilog and VHDL, which may be synthesized and profiled for power using commercial tools. This is the first paper on the PACT compiler project in a series. The compiler framework and introductory optimizations are presented. Later papers will focus on these and other optimizations in detail.

The state of the art of automatic first order logic theorem provers is advanced enough to be useful in a commercial context. This paper describes a way in which first order logic and theorem provers are used at the Swedish formal verification company Safelogic, to formally verify properties of hardware systems. Two different verification methods are discussed, which both make use of translations of formalisms into first order logic. We draw some preliminary conclusions from our experiences and provide problems sets and benchmarks.

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