. In this article we present a structured approach to formal hardware verification by modelling circuits at the register-transfer level using a restricted form of higher-order logic. This restricted form of higher-order logic is sufficient for obtaining succinct descriptions of hierarchically designed register-transfer circuits. By exploiting the structure of the underlying hardware proofs and limiting the form of descriptions used, we have attained nearly complete automation in proving the equivalences of the specifications and implementations. A hardware-specific tool called MEPHISTO converts the original goal into a set of simpler subgoals, which are then automatically solved by a general-purpose, first-order prover called FAUST. Furthermore, the complete verification framework is being integrated within a commercial VLSI CAD framework. Keywords: hardware verification, higher-order logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic com...

We present a new approach to automating the verification of hardware designs based on planning techniques. A database of methods is developed that combines tactics, which construct proofs, using specifications of their behaviour. Given a verification problem, a planner uses the method database to build automatically a specialised tactic to solve the given problem. User interaction is limited to specifying circuits and their properties and, in some cases, suggesting lemmas. We have implemented our work in an extension of the Clam proof planning system. We report on this and its application to verifying a variety of combinational and synchronous sequential circuits including a parameterised multiplier design and a simple computer microprocessor.

We describe the results and status of a project aiming to provide a provably correct library of basic circuits. We use the theorem proving system PVS in order to prove circuits such as incrementers, adders, arithmetic units, multipliers, leading zero counters, shifters, and decoders. All specifications and proofs are available on the web.

An approximate equivalence checking method is developed based on the use of partial Haar spectral diagrams (HSDs). Partial HSDs are defined and used to represent a subset of the Haar spectral coefficients for two functions. Due to the uniqueness properties of the Haar transform, a necessary condition for equivalence is that the individual coefficients must have the same value. The probability that two functions are equivalent is then computed based on the number of observed, same-valued, Haar coefficients. The method described here can be useful for the case where two candidate functions require extreme amounts of computational resources for exact equivalence checking. For simplicity, the technique is explained for the binary case first and extensions to Multiple Valued Logic (MVL) are shown afterwards. Experimental results are provided to validate the effectiveness of this approach. 1. Introduction The equivalence checking problem for two logic functions of n variables, f(X) and g(Y...

Dynamic testing is the process of creating test-vectors during simulation and using the output of the simulator to guide the vector generation process. The two main problems of dynamic testing are the design of a high-level vector-generation language, and the design of the interface between the vector-generator and the simulator. Solutions to these two problems are presented. The paper discusses guidelines for designing a high-level vector generation language, and presents several examples written in the FHDL driver language which was designed according to these guidelines. The examples illustrate how dynamic testing can be used to simplify the verification of circuits at the functional level. The paper presents a solution to the interface problem which is designed around a special interface data structure. This data structure supports several different styles of vector generators and also supports the interactive debugging of circuits. The interface data structure also supports the independent simulation of subcircuit instances and the dynamic creation and

A probabilistic equivalence checking method is developed based on the use of partial Haar spectral diagrams (HSDs). Partial HSDs are defined and used to represent a subset of Haar spectral coefficients for two Boolean functions. The resulting coefficients are then used to compute and to iteratively refine the probability that two functions are equivalent. This problem has applications in both logic synthesis and verification. The method described here can be useful for the case where two candidate functions require extreme amounts of memory for a complete BDD representation. Experimental results are provided to validate the effectiveness of this approach. 1 Introduction The equivalence checking problem for two Boolean functions of n variables, f(X) and g(Y ), is addressed in this work. Here, we assume that the correspondence between the vectors of variables, X and Y is known. Although this problem is easily solved when f and g can be completely represented in BDD form, problems can ar...

Different types of problems in the hardware veri-fication field have inspired different methodologies to tackle them. When different approaches can verify the same class of circuits, at a given level of abstraction, it is often the case that each one has advantages and drawbacks with respect to the others. Comparing dif-ferent methodologies is important, not only to identify the right tool for the right task, but also to evaluate the compromises of different approaches. This paper summarises a comparison between the theorem prov-ing environments HOL and Boyer-Moore, based on a practical experience with both systems for the verifi-cation of a parameterised module from the CATHE DRAL Silicon Compiler library.

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