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A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Three-valued modeling, where the third state X indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete verification. As an extreme case, an N -bit random-access memory (RAM) can be verified by simulating just O(N log N) patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switch-level simulator. By simulating

The aim of this thesis is to investigate the integration of hardware description languages (hdls) and automated proof systems. Simulation of circuit designs written in an hdl is an important method of testing their correctness. However, due to the combinatorial explosion of possible inputs it is not feasible to verify designs using simulation alone. Formal hardware verification, using a proof system, has tried to address this issue. Whilst some medium-sized designs have been (partially) verified, industrial takeup of formal methods has been slow. This is partly due to the use of specialised, non-standard notations employed in various formalisms. By embedding a hardware description language in a proof system we hope to clarify the semantics of the particular hdl, and present a more standard interface to formal methodologies. We have given a new static structural operational semantics for a subset of the ella hardware description language. The formal dynamic semantics of this subset is based on an existing informal model.

Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The model-theoretic properties are exploited to handle the second-order nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripke-style semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...

This report explores the influences of hardware on verifiable secure system design and envisions a mutually beneficial collaboration between the hardware verification and security communities. Hardware verification techniques offer the possibility of significantly enhanced assurance for secure systems at the lowest levels of system design and implementation. Security can provide an important and challenging applications arena in which hardware-oriented formal approaches can be tried and refined. We discuss some of the important concepts and issues that arise in trying to apply formal techniques to secure systems at the hardware level: the meaning of ‘‘security’’ in the context of hardware; the way to identify appropriate security properties at each level of system description, including the hardware level; and, a number of specific concerns related to hardware and its use in secure system development.

Dynamic testing is the process of creating test-vectors during simulation and using the output of the simulator to guide the vector generation process. The two main problems of dynamic testing are the design of a high-level vector-generation language, and the design of the interface between the vector-generator and the simulator. Solutions to these two problems are presented. The paper discusses guidelines for designing a high-level vector generation language, and presents several examples written in the FHDL driver language which was designed according to these guidelines. The examples illustrate how dynamic testing can be used to simplify the verification of circuits at the functional level. The paper presents a solution to the interface problem which is designed around a special interface data structure. This data structure supports several different styles of vector generators and also supports the interactive debugging of circuits. The interface data structure also supports the independent simulation of subcircuit instances and the dynamic creation and