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118
Helios: a hybrid electrical/optical switch architecture for modular data centers
 in ACM SIGCOMM ‘10
"... The basic building block of ever larger data centers has shifted from a rack to a modular container with hundreds or even thousands of servers. Delivering scalable bandwidth among such containers is a challenge. A number of recent efforts promise full bisection bandwidth between all servers, though ..."
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Cited by 88 (15 self)
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The basic building block of ever larger data centers has shifted from a rack to a modular container with hundreds or even thousands of servers. Delivering scalable bandwidth among such containers is a challenge. A number of recent efforts promise full bisection bandwidth between all servers, though with significant cost, complexity, and power consumption. We present Helios, a hybrid electrical/optical switch architecture that can deliver significant reductions in the number of switching elements, cabling, cost, and power consumption relative to recently proposed data center network architectures. We explore architectural trade offs and challenges associated with realizing these benefits through the evaluation of a fully functional Helios prototype.
Silicon Vertically Integrated Nanowire Field Effect Transistors
 Nano
, 2006
"... Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub100nm singlecrystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without t ..."
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Cited by 25 (2 self)
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Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub100nm singlecrystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5nm regime. These firstgeneration vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solidstate nanoelectronic devices. Moore’s law predicts the pace at which transistor dimensions are reduced in order to increase the speed and density of transistors on an integrated circuit. Conventional planar metaloxidesemiconductor FETs (MOSFETs), however, are increasingly facing challenging issues such as shortchannel effects (SCEs), scaling of gate oxide thickness, and increasing power consumption.1 To further miniaturize the transistor while still maintaining control over power consumption,
Overview of Nanoelectronic Devices
 Proceedings of the IEEE
, 1997
"... This paper provides an overview of research developments toward nanometerscale electronic switching devices for use in building ultradensely integrated electronic computers. Specifically, two classes of alternatives to the fieldeffect transistor are considered: 1) quantumeffect and singleelectr ..."
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Cited by 17 (1 self)
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This paper provides an overview of research developments toward nanometerscale electronic switching devices for use in building ultradensely integrated electronic computers. Specifically, two classes of alternatives to the fieldeffect transistor are considered: 1) quantumeffect and singleelectron solidstate devices and 2) molecular electronic devices. A taxonomy of devices in each class is provided, operational principles are described and compared for the various types of devices, and the literature about each is surveyed. This information is presented in nonmathematical terms intended for a general, technically interested readership
Test challenges for deep submicron technologies
 in Proc. 37th Design Automation Conf
, 2000
"... The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying and investigating design challenges in nanometer technologies, the impact on test strategies and methodologies is still n ..."
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Cited by 16 (2 self)
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The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying and investigating design challenges in nanometer technologies, the impact on test strategies and methodologies is still not well understood. This paper highlights the challenges to current test methodologies arising from technology driven trends, and will present an overview of emerging techniques that address deep submicron test challenges. 1.
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling
 DAC
"... Dramatic increase of subthreshold, gate and reverse biased junction bandtobandtunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on ..."
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Cited by 14 (1 self)
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Dramatic increase of subthreshold, gate and reverse biased junction bandtobandtunneling (BTBT) leakage in scaled devices, results in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Current models have been developed based on the exact device geometry, 2D doping profile and operating temperature. A circuit level model of junction BTBT leakage (which is unprecedented) has been developed. Simple models of the subthreshold current and the gate current have been presented. Here, for the first time, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a Sum of Current Sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25nm effective length) at the room and at the elevated temperatures.
Process and Temperature Compensation in a 7MHz CMOS Clock Oscillator
 IEEE J. SolidState Circuits
, 2006
"... Abstract—This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7MHz clock oscillator in a 0.25 m, two–poly fivemetal (2P5M) CMOS process. Measurements made across a temperature range of 40 C to 125 C and 94 samples collected over f ..."
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Cited by 10 (0 self)
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Abstract—This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7MHz clock oscillator in a 0.25 m, two–poly fivemetal (2P5M) CMOS process. Measurements made across a temperature range of 40 C to 125 C and 94 samples collected over four fabrication runs indicate a worst case combined variation of 2.6 % (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95 % of the samples were found to fall within 0.5 % of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was 0.31 % for a supply voltage range of 2.4–2.75 V. The clock generator is based on a threestage differential ring oscillator. The variation of the frequency of the oscillator with temperature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is developed. The biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. A comparator included at the output stage ensures railtorail swing. The oscillator is intended to serve as a startup clock for microcontroller applications. Index Terms—Process compensation, ring oscillators, temperature compensation. I.
Optimal doping profiles via geometric programming
 IEEE Transactions on Electron Devices
, 2005
"... Abstract—We first consider the problem of determining the doping profile that minimizes base transit time in a (homojunction) bipolar junction transistor. We show that this problem can be formulated as a geometric program, a special type of optimization problem that can be transformed to a convex op ..."
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Cited by 2 (1 self)
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Abstract—We first consider the problem of determining the doping profile that minimizes base transit time in a (homojunction) bipolar junction transistor. We show that this problem can be formulated as a geometric program, a special type of optimization problem that can be transformed to a convex optimization problem, and therefore solved (globally) very efficiently. We then consider several extensions to the basic problem, such as accounting for velocity saturation, and adding constraints on doping gradient, current gain, base resistance, and breakdown voltage. We show that a similar approach can be used to maximize the cutoff frequency, taking into account junction capacitances and forward transit time. Finally, we show that the method extends to the case of heterojunction bipolar junction transistors, in which the doping profile, as well as the profile of the secondary semiconductor, are to be jointly optimized. Index Terms—Base doping profile, base transit time minimization, cutoff frequency maximization, geometric programming, Geprofile optimization, optimal doping profile. I.
Device level electrothermal analysis of integrated resistors
 Proc. 14th MIXDES
, 2007
"... ABSTRACT: This paper presents the electrothermal simulation of integrated thin film resistors. Both the thermal and electrical problem is tackled by a semianalytical method, without the need of generating an equivalent distributed network. As the electrical conductivity is temperature dependent, se ..."
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Cited by 2 (1 self)
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ABSTRACT: This paper presents the electrothermal simulation of integrated thin film resistors. Both the thermal and electrical problem is tackled by a semianalytical method, without the need of generating an equivalent distributed network. As the electrical conductivity is temperature dependent, selfheating of the resistor will alterate the current distribution, leading to a nonuniform power dissipation. This then provokes a change of the temperature distribution, explaining the electrothermal coupling. Examples are given for various practical resistor designs. After a few iterations stable values for the electrical and thermal resistance and temperature and power distributions are obtained. The results show that even if one would anticipate the selfheating process based on an estimated average temperature, the behaviour will still deviate from the original design. This is caused entirely by the nonuniformity of the distributions inside the component.
Toward an architectural treatment of parameter variations
, 2005
"... This paper develops a new model of parameter variations for use in earlystage, preRTL architecture studies. It improves over prior models by extending the FMAX model to more faithfully model various microarchitecture structures, especially SRAM, which is dominant in contemporary superscalar proces ..."
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Cited by 2 (1 self)
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This paper develops a new model of parameter variations for use in earlystage, preRTL architecture studies. It improves over prior models by extending the FMAX model to more faithfully model various microarchitecture structures, especially SRAM, which is dominant in contemporary superscalar processors. It also incorporates optical phenomena, which show strong spatial correlation but nevertheless cannot be ignored for large dies. Finally, it incorporates IR Vdd drop and temperature, and closes all these feedback loops to obtain converged estimates of frequency, leakage, voltage, and temperature. With this model, we explore PVT limitations on multicore integration and the difficulties in obtaining matched cores.