This is the nineteenth edition of a (usually) quarterly column that covers new developments in the theory of NP-completeness. The presentation is modeled on that used by M. R. Garey and myself in our book ‘‘Computers and Intractability: A Guide to the Theory of NP-Completeness,’ ’ W. H. Freeman & Co., New York, 1979 (hereinafter referred to as ‘‘[G&J]’’; previous columns will be referred to by their dates). A background equivalent to that provided by [G&J] is assumed, and, when appropriate, cross-references will be given to that book and the list of problems (NP-complete and harder) presented there. Readers who have results they would like mentioned (NP-hardness, PSPACE-hardness, polynomial-time-solvability, etc.) or open problems they would like publicized, should

Physical Mapping is a central problem in molecular biology ... and the human genome project. The problem is to reconstruct the relative position of fragments of DNA along the genome from information on their pairwise overlaps. We show that four simplified models of the problem lead to NP-complete decision problems: Colored unit interval graph completion, the maximum interval (or unit interval) subgraph, the pathwidth of a bipartite graph, and the k-consecutive ones problem for k >= 2. These models have been chosen to reflect various features typical in biological data, including false negative and positive errors, small width of the map and chimericism.

In an edge modification problem one has to change the edge set of a given graph as little as possible so as to satisfy a certain property. We prove the NP-hardness of a variety of edge modification problems with respect to some well-studied classes of graphs. These include perfect, chordal, chain, comparability, split and asteroidal triple free. We show that some of these problems become polynomial when the input graph has bounded degree. We also give a general constant factor approximation algorithm for deletion and editing problems on bounded degree graphs with respect to properties that can be characterized by a finite set of forbidden induced subgraphs.

We study the parameterized complexity of three NP-hard graph completion problems. The MINIMUM FILL-IN problem is to decide if a graph can be triangulated by adding at most k edges. We develop O(c m) and O(k mn + f(k)) algorithms for this problem on a graph with n vertices and m edges. Here f(k) is exponential in k and the constants hidden by the big-O notation are small and do not depend on k. In particular, this implies that the problem is fixed-parameter tractable (FPT). The PROPER

We study two related problems motivated by molecular biology: ffl Given a graph G and a constant k, does there exist a supergraph G of G which is a unit interval graph and has clique size at most k? ffl Given a graph G and a proper k-coloring c of G, does there exist a supergraph We show that those problems are polynomial for fixed k. On the other hand we prove that the first problem is equivalent to deciding if the bandwidth of G is at most k \Gamma 1. Hence, it is NP-hard, and W [t]-hard for all t. We also show that the second problem is W [1]-hard. This implies that for fixed k, both of the problems are unlikely to have an O(n ) algorithm, where ff is a constant independent of k.

In this paper, the gate matrix layout is formulated as a planning problem where a "plan " (the solution steps) is generated to achieve a "goal" (the gate matrix layout) that consists of subgoals interacting each other. Each subgoal corresponds to the placement of a gate to a slot. or to the routing of a net connecting gates. The interaction among subgoals is managed with two AI planning techniques: the hierarchical planning and the mcta-planning. A new distance measure is defined to arrange he. subgoals into pnoritized classes in the hierarchical planning. Two meta-planning policics-gracefd r em and least impact-am used to decide which sub@ IS to be achieved within the same priority class and how it can be achieved. In doing so. GM-Plan successfully combines the gate placement and net routing of the gate matrix layout into one process and has the potential to dcliver better results.

We give an algorithm with runtime O(k 2k n 3 m) for the NP-complete problem [GT35 in 6] of deciding whether a graph on n vertices and m edges can be turned into an interval graph by adding at most k edges. We thus prove that this problem is fixed parameter tractable (FPT), settling a long-standing open problem [13, 5, 19, 11]. The problem has applications in Physical Mapping of DNA [9] and in Profile Minimization for Sparse Matrix Computations [7, 20]. For the first application, our results show tractability for the case of a small number k of false negative errors, and for the second, a small number k of zero elements in the envelope.

This paper was written during a visit of the second author to LIP-IMAG/ENS Lyon. 2 Afonso G. Ferreira and Siang W. Song

Abstract not found

Abstract. A linear arrangement problem, called the minmax mincut problem, emerging from circuit design is investigated. Its input is a series-parallel directed hypergraph (SPDH), and the output is a linear arrangement (and a layout). The primary objective is to minimize the longest path, and the secondary objective is to minimize the cutwidth. It is shown that cutwidth D, subject to longest path minimization, is affected by two terms: pattern number k and balancing number m. Also, k and m are both lower bounds on the cutwidth. An algorithm, running in linear time, produces layouts with cutwidths D ≤ 2(k + m). There exist examples with k =Ω(N), where N is the number of vertices; however, m is always O(log N). We show that every SPDH, after local logic resynthesis (specifically, after reordering the serial paths), can be linearly placed with cutwidth D = O(log N). Simultaneously, its dual SPDH can be linearly placed with the same vertex order and with cutwidth D = O(log N). Therefore, after local resynthesis the area can be reduced by a factor of N/log N. Application to gate-matrix layout style is demonstrated. Key words. VLSI design, linear arrangement, graphs and large scale networks, resynthesis, timing, VLSI layout