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Equivalence Checking of Integer Multipliers
 In Proceedings of ASPDAC '2001
, 2001
"... In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut poin ..."
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In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut points and thus dramatically improve the backward substitution process, (2) a layeredbackward substitution algorithm to reduce the number of substitutions, and (3) Multiplicative Power Hybrid Decision Diagrams (*PHDDs) as our wordlevel representation rather than *BMD in Hamaguchi's approach. Experimental results show that our approach can efficiently check the equivalence of two integer multipliers. To verify the equivalence of a array multiplier versus a Wallace tree multiplier, our approach takes about 57 CPU seconds using 11 Mbytes, while Stanion's approach took 21027 seconds using 130 MBytes. We also show that the complexity of our approach is upper bounded by 31 , where is the word size, but our experimental results show that the complexity of our approach grows cubically lly .
Manipulation of *BMDs
 In Asian and SouthPacific Design Automation Conference
, 1998
"... Multiplicative Binary Moment Diagrams (*BMDs) have recently been introduced as a data structure for verification. Using *BMDs it was for the first time possible to verify multiplier circuits with up to 256 bits. In this paper we use a modification of *BMDs, called positive *BMDs (p*BMDs), that allow ..."
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Multiplicative Binary Moment Diagrams (*BMDs) have recently been introduced as a data structure for verification. Using *BMDs it was for the first time possible to verify multiplier circuits with up to 256 bits. In this paper we use a modification of *BMDs, called positive *BMDs (p*BMDs), that allows to apply dynamic variable ordering, that is the most promising minimization technique for decision diagrams, to *BMDs. Furthermore, we study *BMDs representing Boolean functions. We show that in this case for some operations polynomial algorithms can be given, while the general case of integervalued functions requires exponential effort. Experimental results demonstrate that p*BMDs clearly outperform *BMDs with respect to runtime during dynamic minimization, while keeping (nearly) all advantages. I. Introduction Most formal approaches in verification nowadays make use of function representation by Decision Diagrams (DDs). In this context Ordered Binary Decision Diagrams (OBDDs) [4] hav...
Equivalence Checking of Arithmetic Circuits on the Arithmetic Bit Level
 IEEE Trans. on CAD of Integrated Circuits and Systems
, 2004
"... Abstract—One of the most sev ere shortcomings of currently av ailable equiv alence checkers is their inability to v erify arithmetic circuits and multipliers, in particular. In this paper, we present a bitlev el rev erseengineering technique that complements standard equiv alence checking framewor ..."
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Abstract—One of the most sev ere shortcomings of currently av ailable equiv alence checkers is their inability to v erify arithmetic circuits and multipliers, in particular. In this paper, we present a bitlev el rev erseengineering technique that complements standard equiv alence checking frameworks. W e propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bitlev el representation of the circuit is obtained, equiv alence checking can be performed using simple arithmetic operations. W e hav e successfully applied the technique for the v erification of a large number of multipliers of different architectures as well as more general arithmetic circuits, such as multiply/add units. The experimental results show the great promise of our approach. Index T erms—Arithmetic bit lev el, arithmetic circuit, datapath v erification, equiv alence checking, formal hardware v erification, multiplier. I.
Prove That a Faulty Multiplier is Faulty!?
, 1999
"... Formal verification of integer multipliers was an open problem for a long time as the size of any reduced ordered binary decision diagram (BDD) [1] which represents integer multiplication is exponential in the width of the operands [2]. In 1995, Bryant and Chen [4] introduced multiplicative binary m ..."
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Formal verification of integer multipliers was an open problem for a long time as the size of any reduced ordered binary decision diagram (BDD) [1] which represents integer multiplication is exponential in the width of the operands [2]. In 1995, Bryant and Chen [4] introduced multiplicative binary moment diagrams (*BMD) which is a canonical data structure for pseudo Boolean functions allowing a linear representation of integer multipliers. Based on this data structure, Bryant/Chen [4] and Hamaguchi et.al. experimentally showed [5] that integer multipliers up to a word size of 64 bits can be formally verified. However, all these results only handle the problem of proving a faultless integer multiplier to be correct. But, what happens if the multiplier is faulty? Does the backward construction method stop after a short time? After what time can I be sure that the integer multiplier under consideration is faulty? In this paper, we show that these questions are relevant in practice. In particular, we investigate simple addstep multipliers and show that simple design errors can lead to exponential growth of the *BMDs occuring during backward construction. This proves that the backward construction method can only be applied as filter during formal logic combinational verification unless sharp upper bounds for the sizes of the *BMDs occuring during the backward construction have been proven for the various circuit types as Keim et.al. [6] did it for Wallace Tree multipliers.
SelfReferential Verification of GateLevel Implementations of Arithmetic Circuits
, 2002
"... Verification of gatelevel implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hardtoverify arithmetic operators (e.g. multiplication), the use of different operand ordering, the incorporation of merged arithmetic with crossoperator implementati ..."
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Verification of gatelevel implementations of arithmetic circuits is challenging due to a number of reasons: the existence of some hardtoverify arithmetic operators (e.g. multiplication), the use of different operand ordering, the incorporation of merged arithmetic with crossoperator implementations, and the employment of circuit transformations based on arithmetic relations. It is hence a peculiar problem that does not fit quite well into the existing RTLto gate equivalence checking methodology. In this paper, we propose a selfreferential functional verification approach which uses the gatelevel implementation of the arithmetic circuit under verification to verify itself. Specifically, the verification task is decomposed into a sequence of equivalence checking subproblems, each of which compare circuit pairs derived from the implementation under verification based on the proposed selfreferential functional equations. A decompositionbased heuristic using structural information is employed to guide the verification process for better efficiency. Experimental results on a number of implementations of the multiplyadd units and the inner product units with different architectures demonstrate the versatility of this approach.
Symbolic Topological Sorting with OBDDs (Extended Abstract)
"... Abstract. We present a symbolic OBDD algorithm for topological sorting which requires O(log 2 N) OBDD operations. Then we analyze its true runtime for the directed grid graph and show an upper bound of O(log 4 N). This is the first true runtime analysis of a symbolic OBDD algorithm for a fundamental ..."
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Abstract. We present a symbolic OBDD algorithm for topological sorting which requires O(log 2 N) OBDD operations. Then we analyze its true runtime for the directed grid graph and show an upper bound of O(log 4 N). This is the first true runtime analysis of a symbolic OBDD algorithm for a fundamental graph problem, and it demonstrates that one can hope that the algorithm behaves well for sufficiently structured inputs. 1
Lower Bounds on the OBDD Size of Graphs of Some Popular Functions ⋆
"... Abstract. Ordered binary decision diagrams (OBDDs) are a data structure for Boolean functions which supports many useful operations. It finds many applications in logic design, CAD, model checking, and symbolic graph algorithms. Nevertheless, many simple functions are known to have exponential OBDD ..."
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Abstract. Ordered binary decision diagrams (OBDDs) are a data structure for Boolean functions which supports many useful operations. It finds many applications in logic design, CAD, model checking, and symbolic graph algorithms. Nevertheless, many simple functions are known to have exponential OBDD size w. r. t. their number of variables. In order to investigate the limits of symbolic graph algorithms which work on OBDDrepresented graph instances, it is useful to have simplystructured graphs whose OBDD representation has exponential size. Therefore, we consider fundamental arithmetic and storage access functions with exponential OBDD size and transfer these results to the graphs of these functions. Concretely, lower bounds for the graphs of integer multiplication, indirect storage access, and the hidden weighted bit function are presented. Finally, an exemplary application of the result for multiplication to the analysis of a symbolic allpairs shortestpaths algorithm is discussed. 1