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Verification of analog/mixedsignal circuits using labeled hybrid petri nets
 IN: PROC. OF ICCAD
, 2006
"... System on a chip design results in the integration of digital, analog, and mixedsignal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling s ..."
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Cited by 19 (9 self)
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System on a chip design results in the integration of digital, analog, and mixedsignal circuits on the same substrate which further complicates the already difficult validation problem. This paper presents a new model, labeled hybrid Petri nets (LHPNs), that is developed to be capable of modeling such a heterogeneous set of components. This paper also describes a compiler from VHDLAMS to LHPNs. To support formal verification, this paper presents an efficient zonebased state space exploration algorithm for LHPNs. This algorithm uses a process known as warping to allow zones to describe continuous variables that may be changing at variable rates. Finally, this paper describes the application of this algorithm to a couple of analog/mixedsignal circuit examples.
Verification of Analog and MixedSignal Circuits Using Symbolic Methods
, 2007
"... Abstract. Embedded systems are composed of a heterogeneous collection of digital, analog, and mixedsignal hardware components. This paper presents a method for the verification of systems composed of such a variety of components. This method utilizes a new model, timed hybrid Petri nets (THPN), to ..."
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Cited by 14 (5 self)
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Abstract. Embedded systems are composed of a heterogeneous collection of digital, analog, and mixedsignal hardware components. This paper presents a method for the verification of systems composed of such a variety of components. This method utilizes a new model, timed hybrid Petri nets (THPN), to model these circuits. In particular, this paper describes an efficient, approximate algorithm to find the reachable states of a THPN model. Using this state space, desired properties specified in ACTL are verified. To demonstrate these methodologies, a few hybrid automata benchmarks, a tunnel diode oscillator, and a phaselocked loop are modeled and analyzed using THPNs. 1
A Mechanized Refinement Framework for Analysis of Custom Memories
"... Abstract — We present a framework for formal verification of embedded custom memories. Memory verification is complicated by the difficulty in abstracting design parameters induced by the inherently analog nature of transistorlevel designs. We develop behavioral formal models that specify a memory ..."
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Cited by 3 (1 self)
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Abstract — We present a framework for formal verification of embedded custom memories. Memory verification is complicated by the difficulty in abstracting design parameters induced by the inherently analog nature of transistorlevel designs. We develop behavioral formal models that specify a memory as a system of interacting read/write view of the memory via refinements. The operating constraints on the individual state machines can be validated by readily available data from analog simulations. The framework handles both static RAM (SRAM) and flash memories, and we show initial results demonstrating its applicability. I.
ProjectagonBased Reachability Analysis for CircuitLevel Formal Verification
, 2011
"... This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications include consumer electronics, telecommunications, medical electronics. Furthermore, in deep submicron design, physical effects might undermine common ..."
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This dissertation presents a novel verification technique for analog and mixed signal circuits. Analog circuits are widely used in many applications include consumer electronics, telecommunications, medical electronics. Furthermore, in deep submicron design, physical effects might undermine common digital abstractions of circuit behavior. Therefore, it is necessary to develop systematic methodologies to formally verify hardware design using circuitlevel models. We present a formal method for circuitlevel verification. Our approach is based on translating verification problems to reachability analysis problems. It applies nonlinear ODEs to model circuit dynamics using modified nodal analysis. Forward reachable regions are computed from given initial states to explore all possible circuit behaviors. Analog properties are checked on all circuit states to ensure full correctness or find a design flaw. Our specification language extends LTL logic with continuous time and values and applies Brockett’s annuli to specify analog signals. We also introduced probability into the specification to support practical analog properties such as metastability behavior.
in Computer Aided Design
, 2007
"... al M ethods in C om puter A ided D esign Proceedings ..."
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Abstracting and Verifying Flash Memories
"... Abstract—We present a framework for formal verification of flash cores. Flash memories cannot be verified by traditional switchlevel abstractions, due to capacitive coupling induced by the presence of floating gates. We discuss a new approach to abstracting transistor networks that is agnostic to t ..."
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Abstract—We present a framework for formal verification of flash cores. Flash memories cannot be verified by traditional switchlevel abstractions, due to capacitive coupling induced by the presence of floating gates. We discuss a new approach to abstracting transistor networks that is agnostic to the type of transistor used in the implementation. We show how to use this abstraction to model flash memory designs. The abstractions are used for functional verification of memory cores, and can be validated through analog simulation. We have used the approach in the verification of representative NOR and a NAND flash memory cores. I.
Qualification of Behavioral Level Design Validation
, 2008
"... The expansion of Wireless SystemsonChip leads to a rapid development of design and manufacturing methods. In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on var ..."
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The expansion of Wireless SystemsonChip leads to a rapid development of design and manufacturing methods. In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on variation of behavioral parameters and a related qualification metric are proposed. This approach is used in the receiver’s design of a WCDMA transceiver. A test set defined by verification engineers during the validation of this system is qualified and optimized. Then, this test set is compared with a second test set automatically generated by a developed tool.
Date Approved
, 2013
"... This document describes an improved method of formal verification of complex analog/mixedsignal (AMS) circuits. Currently, in our LEMA tool, verification properties are encoded using labeled Petri net (LPN). These LPNs are generated manually, a tedious process that requires the user to have consid ..."
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This document describes an improved method of formal verification of complex analog/mixedsignal (AMS) circuits. Currently, in our LEMA tool, verification properties are encoded using labeled Petri net (LPN). These LPNs are generated manually, a tedious process that requires the user to have considerable familiarity with the tool. To eliminate this timeconsuming process, our LEMA tool is extended to include a translator that converts properties written in a property specification language to LPNs. New methods are also implemented to separate the transient period from the stable output period, thus improving the generated model. Also, the current methodology generates the circuit models for the input values used during the simulation of the circuit. So, models generated for other control input values are not accurate. In this case, accuracy of the generated models is improved by using a linear abstraction method like interpolation. To my advisor, Chris
FAC 2005 Preliminary Version The Case for Analog Circuit Verification
"... The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple exampl ..."
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The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases have been simulated. A new alternative is to utilize formal verification techniques. This paper utilizes a simple example to illustrate the potential flaws of a simulationonly based validation methodology and the potential benefits of formal verification of analog circuits. Key words: Analog circuits, formal verification, hybrid Petri nets
Formal Verification of Analog Designs using
"... Abstract—MetiTarski, an automatic theorem prover for inequalities on realvalued elementary functions, can be used to verify properties of analog circuits. First, a closed form solution to the model of the circuit is obtained. We present two techniques for obtaining the closed form solution. One is ..."
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Abstract—MetiTarski, an automatic theorem prover for inequalities on realvalued elementary functions, can be used to verify properties of analog circuits. First, a closed form solution to the model of the circuit is obtained. We present two techniques for obtaining the closed form solution. One is based on piecewise linear modeling and the inverse Laplace transform. The other is based on smallsignal analysis and transfer function theory. Second, the properties of interest are turned into a set of inequalities involving analytic functions, which are proved automatically using MetiTarski. We verify properties concerning oscillation and the change in gain due to component tolerances. I.