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Analog/MixedSignal Circuit Verification Using Models Generated from Simulation Traces ⋆
"... Abstract. Formal and semiformal verification of analog/mixedsignal circuits is complicated by the difficulty of obtaining circuit models suitable for analysis. We propose a method to generate a formal model from simulation traces. The resulting model is conservative in that it includes all of the ..."
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Abstract. Formal and semiformal verification of analog/mixedsignal circuits is complicated by the difficulty of obtaining circuit models suitable for analysis. We propose a method to generate a formal model from simulation traces. The resulting model is conservative in that it includes all of the original simulation traces used to generate it plus additional behavior. Information obtained during the model generation process can also be used to refine the simulation and verification process. 1
Abstract Modeling and Simulation Aided Verification of Analog/MixedSignal Circuits
, 2008
"... Abstract. Analog/Mixedsignal (AMS) circuit verification is a growing problem as process variation increases and AMS circuits become more functionally complex. To improve analog verification flows, AMS circuit models are needed at different levels of abstraction. This paper discusses recent work and ..."
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Abstract. Analog/Mixedsignal (AMS) circuit verification is a growing problem as process variation increases and AMS circuits become more functionally complex. To improve analog verification flows, AMS circuit models are needed at different levels of abstraction. This paper discusses recent work and future directions for abstract model generation and simulation aided verification of AMS circuits. In particular, a CMOS ring oscillator with feedforward inverters is used as a motivating example for the work. This example highlights progress and future directions in AMS modeling and verification. 1
Bounded Model Checking of Analog and MixedSignal Circuits Using an SMT Solver ⋆
"... Abstract. This paper presents a bounded model checking algorithm for the verification of analog and mixedsignal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The systems are modeled in VHDLAMS, a hardware description language for AMS circuits. In this model, system safety pro ..."
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Abstract. This paper presents a bounded model checking algorithm for the verification of analog and mixedsignal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The systems are modeled in VHDLAMS, a hardware description language for AMS circuits. In this model, system safety properties are specified as assertion statements. The VHDLAMS description is compiled into labeled hybrid Petri nets (LHPNs) in which analog values are modeled as continuous variables that can change at rates in a bounded range and digital values are modeled using Boolean signals. The verification method begins by transforming the LHPN model into an SMT formula composed of the initial state, the transition relation unrolled for a specified number of iterations, and the complement of the assertion in each set of state variables. When this formula evaluates to true, this indicates a violation of the assertion and an error trace is reported. This method has been implemented and preliminary results are promising. 1
DC Operating Point Analysis – A Formal Approach
"... Abstract. If the inputs to a circuit are held constant, then the state of some circuits settle to a unique equilibrium: the DC operating point. Many circuit analysis techniques seek to determine or use this state and assume that it is unique. However, for some constant input some circuits may settle ..."
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Abstract. If the inputs to a circuit are held constant, then the state of some circuits settle to a unique equilibrium: the DC operating point. Many circuit analysis techniques seek to determine or use this state and assume that it is unique. However, for some constant input some circuits may settle to one of several different operating points, while still others may never settle. In this paper we describe a procedure that uses symbolic circuit models generated from a netlist level circuit description to rigorously locate and classify all of the equilibria of a circuit model in order to determine the existence, location and number of DC operating points. Implemented with a collection of public tools (HySAT, INTLAB and EigTool) and our own MATLAB circuit modeling system OOmspice, we demonstrate that the technique can deduce the hysteresis of a Schmitt trigger and the lack of DC operating points for a ring oscillator with an odd number of stages. 1
Formal Verification of PhaseLocked Loops Using Reachability Analysis and Continuization
"... Wepresentanapproachfor verifyinglockingofchargepump phaselocked loops by performing reachability analysis on a behavioral model of the circuit. Bounded uncertain parameters in the behavioral model make it possible to represent all possible behaviors of more detailed models. The dynamics of the beh ..."
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Wepresentanapproachfor verifyinglockingofchargepump phaselocked loops by performing reachability analysis on a behavioral model of the circuit. Bounded uncertain parameters in the behavioral model make it possible to represent all possible behaviors of more detailed models. The dynamics of the behavioral model is hybrid (i.e., discrete and continuous) due to the switching of charge pumps that drive the analog control circuits. A unique feature of phaselocked loops compared to most other hybrid systems is that they require thousands of switchings in the continuous dynamics to converge sufficiently close to a limit cycle. This makes reachability analysis a challenging task since switches in the dynamics are expensive to compute and result in conservative overapproximations. We solve this problem by overapproximating the effects of the switching conditions with uncertain parameters inlinear continuousmodels, amethodwe call continuization. Using efficient reachability algorithms for discretetime linear systems, locking is verified over the complete range of possible initial states of a chargepump PLL designed in 32nm CMOS SOI technology in comparable time required for Monte Carlo simulations of the same behavioral model. 1.
A New Verification Method For Embedded Systems
"... Abstract — Verification of embedded systems is complicated by the fact that they are composed of digital hardware, analog sensors and actuators, and low level software. In order to verify the interaction of these heterogeneous components, it would be beneficial to have a single modeling formalism th ..."
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Abstract — Verification of embedded systems is complicated by the fact that they are composed of digital hardware, analog sensors and actuators, and low level software. In order to verify the interaction of these heterogeneous components, it would be beneficial to have a single modeling formalism that is capable of representing all of these components. To address this need, this paper describes an extended labeled hybrid Petri net (LHPN) model that includes constructs for Boolean, discrete, and continuous variables as well as constructs to model timing. This paper also presents a method to verify these extended LHPNs. Finally, this paper presents a case study to illustrate the application of this model to the verification of a faulttolerant temperature sensor. I.
Piecewise Linear Modeling of Nonlinear devices for Formal Verification of Analog Circuits
"... Abstract—We consider different piecewise linear (PWL) models for nonlinear devices in the context of formal DC operating point and transient analyses of analog circuits. PWL models allow us to encode a verification problem as constraints in linear arithmetic, which can be solved efficiently using mo ..."
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Abstract—We consider different piecewise linear (PWL) models for nonlinear devices in the context of formal DC operating point and transient analyses of analog circuits. PWL models allow us to encode a verification problem as constraints in linear arithmetic, which can be solved efficiently using modern SMT solvers. Numerous approaches to piecewise linearization are possible, including piecewise constant, simplicial piecewise linearization and canonical piecewise linearization. We address the question of which PWL modeling approach is the most suitable for formal verification by experimentally evaluating the performance of various PWL models in terms of running time and accuracy for the DC operating point and transient analyses of several analog circuits. Our results are quite surprising: piecewise constant (PWC) models, the simplest approach, seem to be the most suitable in terms of the tradeoff between modeling precision and the overall analysis time. Contrary to expectations, more sophisticated device models do not necessarily provide significant gains in accuracy, and may result in increased running time. We also present evidence suggesting that PWL models may not be suitable for certain transient analyses. I.
Proving and Explaining the Unfeasibility of Message Sequence Charts for Hybrid Systems
"... Abstract—Networks of Hybrid Automata are a clean modelling framework for complex systems with discrete and continuous dynamics. Message Sequence Charts (MSCs) are a consolidated languagetodescribedesiredbehaviorsofanetworkofinteracting components. Techniques to analyze the feasibility of an MSC over ..."
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Abstract—Networks of Hybrid Automata are a clean modelling framework for complex systems with discrete and continuous dynamics. Message Sequence Charts (MSCs) are a consolidated languagetodescribedesiredbehaviorsofanetworkofinteracting components. Techniques to analyze the feasibility of an MSC over a given HA network are based on specialized bounded model checking techniques, and focus on efficiently constructing traces of the network that witness the MSC behavior. Unfortunately, these techniques are unable to deal with the “unfeasibility ” of the MSC, i.e. that no trace of the network satisfies the MSC. In this paper, we tackle the problem of MSC unfeasibility: first, we propose specialized techniques to prove that an MSC can not be satisfied by any trace of a given HA network; second, we show how to explain why an MSC is unfeasible. The approach is cast in an SMTbased verification framework, usingalocaltimesemantics,wherethetimescalesoftheautomata in the network are synchronized upon shared events. In order to prove unfeasibility, we generalize kinduction to deal with the structure of the MSC, so that the simple path condition is localized to each fragment of the MSC. The explanations are provided as formulas in the variables representing the time points of the events of the MSCs, and are generated using unsatisfiable core extraction and interpolation. An experimental evaluation demonstrates the effectiveness of the approach in proving unfeasibility, and the adequacy of the automatically generated explanations. I.
Date Approved
, 2011
"... Verification of analog circuits is becoming a bottleneck for the verification of complex analog/mixedsignal (AMS) circuits. In order to assist functional verification of complex AMS systemonchips (SoCs), there is a need to represent the transistorlevel circuits in the form of abstract models. T ..."
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Verification of analog circuits is becoming a bottleneck for the verification of complex analog/mixedsignal (AMS) circuits. In order to assist functional verification of complex AMS systemonchips (SoCs), there is a need to represent the transistorlevel circuits in the form of abstract models. The ability to represent the analog circuits as behavioral models is necessary, but not sufficient. Though there exist languages like VerilogAMS and VHDLAMS for modeling AMS circuits, there is no easy method for generating these models directly from the transistorlevel descriptions. This thesis presents an improved method for extracting behavioral models from the simulations of AMS circuits. This method generates labeled Petri net (LPN) models that can be used in the formal verification of circuits, and SystemVerilog models that can be used in the systemlevel simulations. To my advisor, ChrisCONTENTS