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28
A 32bit Logarithmic Arithmetic Unit and Its Performance Compared to FloatingPoint
 14TH SYMPOSIUM ON COMPUTER ARITHMETIC
, 1999
"... As an alternative to floatingpoint, several papers have proposed the use of a logarithmic number system, in which a real number is represented as a fixedpoint logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an over ..."
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Cited by 15 (2 self)
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As an alternative to floatingpoint, several papers have proposed the use of a logarithmic number system, in which a real number is represented as a fixedpoint logarithm. Multiplication and division therefore proceed in minimal time with no rounding error. However, the system can only offer an overall advantage if addition and subtraction can be performed with speed and accuracy at least equal to that of floatingpoint, but these operations require the interpolation of a nonlinear function which has hitherto been either timeconsuming or inaccurate. We present a procedure by which additions and subtractions can be performed rapidly and accurately, and show that these operations are thereby competitive with their floatingpoint equivalents. We then show that the average performance of the logarithmic system exceeds floatingpoint, in terms of both speed and accuracy.
Embedded Model Predictive Control for SystemonaChip Applications
 Journal of Process Control
, 2004
"... Abstract: We propose a framework for embedding model predictive control for SystemsonaChip applications. In order to allow the implementation of such a computationally expensive controller on chip, we propose reducing the precision of the operations coupled with using logarithmic number system ar ..."
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Cited by 14 (7 self)
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Abstract: We propose a framework for embedding model predictive control for SystemsonaChip applications. In order to allow the implementation of such a computationally expensive controller on chip, we propose reducing the precision of the operations coupled with using logarithmic number system arithmetic. Two particular control problems are examined. We provide the methodology for choosing the design parameters; we emulate the performance of the embedded controller for the examined cases and we give the microprocessor architecture details. Keywords: Embedded Systems, Model Predictive Control, SystemsonaChip. 1.
LNS Architectures for Embedded Model Predictive Control Processors
 Processors,” in International Conference on Compilers, Architectures and Synthesis for Embedded Systems, (in press
, 2004
"... This paper presents a research on arithmetic units targeted to implement model predictive control (MPC) in a custom embedded processor. A novel hardware implementation of cotransformation for the calculation of addition and subtraction in the Logarithmic Number System (LNS) is proposed. This archite ..."
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Cited by 12 (6 self)
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This paper presents a research on arithmetic units targeted to implement model predictive control (MPC) in a custom embedded processor. A novel hardware implementation of cotransformation for the calculation of addition and subtraction in the Logarithmic Number System (LNS) is proposed. This architecture provides a small ROMless adder/subtracter, with longer operation latency than other LNStechniques, but easily pipelineable. These characteristics make it very adequate for implementing the datapath of custom MPC embeddable microprocessors. A review of the arithmetic customization process is presented, including: an analysis of the finite precision problem, modifications to the standard MPC algorithm that simplify embedding the application, and the reasons that suggest better performance of LNSover standard floatingpoint (FP) architectures. The proposed arithmetic unit architecture for 16bit LNSis fully synthesized for ASIC, and compared with an equivalent FP implementation. Area and clock cycle estimates are compared. Finally, considerations on lowprecision implementations of LNSarithmetic units are provided, and an embeddedROM implementation of addition/subtraction in LNSis proposed and analyzed.
Handbook of FloatingPoint Arithmetic
, 2009
"... REPRESENTING AND MANIPULATING real numbers efficiently is required in many fields of science, engineering, finance, and more. Since the early years of electronic computing, many different ways of approximating real numbers on computers have been introduced. One can cite (this list is far ..."
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Cited by 8 (6 self)
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REPRESENTING AND MANIPULATING real numbers efficiently is required in many fields of science, engineering, finance, and more. Since the early years of electronic computing, many different ways of approximating real numbers on computers have been introduced. One can cite (this list is far
Complex Logarithmic Number System Arithmetic Using HighRadix Redundant CORDIC Algorithms
 Proc. 14th IEEE Symposium on Computer Arithmetic Adelaide, Australia
, 1999
"... This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with approximately the same hardware as a highradix CORDIC operation. A design example comparable to single precision floati ..."
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Cited by 7 (0 self)
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This paper describes the application of high radix redundant CORDIC algorithms to complex logarithmic number system arithmetic. It shows that a CLNS addition can be performed with approximately the same hardware as a highradix CORDIC operation. A design example comparable to single precision floating point has been
Reduced Power Consumption for MPEG Decoding with LNS
 APPLICATIONSPECIFIC SYST., ARCH., PROC. (ASAP), IEEE
, 2002
"... ..."
A DualPurpose Real/Complex Logarithmic Number System ALU
 19TH IEEE INTERNATIONAL SYMPOSIUM ON COMPUTER ARITHMETIC
, 2009
"... The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higherorder and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented e ..."
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Cited by 6 (3 self)
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The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higherorder and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented effectively on FPGAs for a wide variety of mediumprecision specialpurpose applications. The Complex LNS (CLNS) is a generalization of LNS which represents complex values in logpolar form. CLNS is a more compact representation than traditional rectangular methods, reducing the cost of busses and memory in intensive complexnumber applications like the FFT; however, prior CLNS implementations were either slow CORDICbased or expensive 2Dtablebased approaches. This paper attempts to leverage the recent advances made in realvalued LNS units for the more specialized context of CLNS. This paper proposes a novel approach to reduce the cost of CLNS addition by reusing a conventional realvalued LNS ALU with specialized CLNS hardware that is smaller than the realvalued LNS ALU to which it is attached. The resulting ALU is much less expensive than prior fast CLNS units at the cost of some extra delay. The extra hardware added to the ALU is for trigonometricrelated functions, and may be useful in LNS applications other than CLNS. The novel algorithm proposed here is implemented using the FloPoCo library (which incorporates recent HOTBM advances in functionunit generation), and FPGA synthesis results are reported.
A SingleMultiplier Quadratic Interpolator for LNS Arithmetic
 PROC. 2001 IEEE INTL. CONF. ON COMPUTER DESIGN: ICCD 2001
, 2001
"... Linear interpolation requires a single multiplication but is significantly less accurate than quadratic interpolation. The latter requires two multiplications. Two novel quadratic interpolation schemes are shown here that approximate the functions required by the Logarithmic Number System (LNS) with ..."
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Cited by 5 (2 self)
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Linear interpolation requires a single multiplication but is significantly less accurate than quadratic interpolation. The latter requires two multiplications. Two novel quadratic interpolation schemes are shown here that approximate the functions required by the Logarithmic Number System (LNS) with more accuracy than linear interpolation using only a single multiplication. One method uses two ROMs to give the accuracy of quadratic interpolation, whilst the other uses one ROM to give four to sixbits better accuracy than linear interpolation. These techniques save four to eightfold on memory compared to linear interpolation for the same accuracy. We illustrate the usefulness of these techniques for serial implementation with a clone of the ARM TM microprocessor (known as AWE) that we developed to have LNS instructions. We also
Cotransformation Provides Area and Accuracy Improvement in an
 HDL Library for LNS Subtraction,” Accepted for The EuroMicro Conference on Digital Systems and Design
, 2007
"... The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) attractive. Addition and subtraction, though, are the bottleneck of every LNS circuit, for which there are implementation ..."
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Cited by 3 (3 self)
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The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) attractive. Addition and subtraction, though, are the bottleneck of every LNS circuit, for which there are implementation techniques that tradeoff area, latency and accuracy. This paper reviews the methods of interpolation, multipartite tables and cotransformation for LNS addition and subtraction, but special focus is given on a novel version of cotransformation, for which a new special case is identified. Synthesis results compare an already published Hardware Description Language (HDL) library for LNS arithmetic that uses only multipartite tables or 2 ndorder interpolation against a variation of the same library combined with cotransformation. Exhaustive simulation and a graphics example illustrate that the proposed library has smaller area requirements and is more accurate than the earlier library, at the cost of an increase in the latency of the hardware. Track: Programmable/reconfigurable architectures (Computer Arithmetic)