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Model Checking Partially Ordered State Spaces
, 1995
"... The state explosion problem is the fundamental limitation of verification through model checking. In many cases, representing the state space of a system as a lattice is an effective way of ameliorating this problem. The partial order of the state space lattice represents an information ordering. Th ..."
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Cited by 16 (3 self)
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The state explosion problem is the fundamental limitation of verification through model checking. In many cases, representing the state space of a system as a lattice is an effective way of ameliorating this problem. The partial order of the state space lattice represents an information ordering. The paper shows why using a lattice structure is desirable, and why a quaternary temporal logic rather than a traditional binary temporal logic is suitable for describing properties in systems represented this way. The quaternary logic not only has necessary technical properties, it also expresses degrees of truth. This is useful to do when dealing with a state space with an information ordering defined on it, where in some states there may be insufficient or contradictory information available. The paper presents the syntax and semantics of a quaternary valued temporal logic. Symbolic trajectory evaluation (STE) [32] has been used to model check partially ordered state spaces with some succes...
Formalizing Java's Two'sComplement Integral Type in Isabelle/HOL
 In Eighth International Workshop on Formal Methods for Industrial Critical Systems (FMICS’03). ENTCS 80
, 2003
"... We present a formal model of the Java two'scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointe ..."
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Cited by 2 (1 self)
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We present a formal model of the Java two'scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointed out and clarified. The theory is formally analyzed in Isabelle/HOL, that is, machinechecked proofs for the ring properties and divisor/remainder theorems etc. are provided. This work is suited to build the framework for machinesupported reasoning over arithmetic formulae in the context of Java sourcecode verification.
Exploring Multiplier Architecture and Layout
"... Multiplication represents a fundamental building block in all DSP tasks. Due to the large latency inherent in multiplication, schemes have been devised to minimize the delay. Two methods are common in current implementations: regular arrays and Wallace trees. Previous gatelevel analyses have sugges ..."
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Multiplication represents a fundamental building block in all DSP tasks. Due to the large latency inherent in multiplication, schemes have been devised to minimize the delay. Two methods are common in current implementations: regular arrays and Wallace trees. Previous gatelevel analyses have suggested that not only are Wallace trees faster than array schemes, they also consume much less power. However these analyses did not take wiring into account, resulting in optimistic timing and power estimates. We develop a simplified comparative layout methodology to analyze the effect of physical layout on these designs. Results for short bitwidth (8, 16, 24 bit) DSP multipliers show that while wiring has a major impact on signal delay and power, Wallace trees still show roughly a 10 % power advantage over arraybased designs.
18 pages Formalizing Java’s Two’sComplement Integral Type in Isabelle/HOL
"... We present a formal model of the Java two’scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointe ..."
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We present a formal model of the Java two’scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointed out and clarified. The theory is formally analyzed in Isabelle/HOL, that is, machinechecked proofs for the ring properties and divisor/remainder theorems etc. are provided. This work is suited to build the framework for machinesupported reasoning over arithmetic formulae in the context of Java sourcecode verification.
A ReducedBit Multiplication Algorithm for Digital Arithmetic
"... Abstract—A reducedbit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally ..."
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Abstract—A reducedbit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bitshifting to take advantage of bitreduction in multiplication. We illustrate the proposed algorithm by reducing a general 4 × 4bit multiplication to a single 2 × 2bit multiplication operation. Keywords—Multiplication, algorithm, Vedic mathematics, digital arithmetic, reducedbit.
Delay Comparison of 4 by 4 Vedic Multiplier based on Different Adder Architectures using VHDL
"... This paper presents a delay comparison of two different multipliers for unsigned data, one uses a ripple carry and the second one uses a carrylookahead adder. The 4×4 Vedic multiplier module using Urdhva Tiryakbhyam Sutra uses four 2×2 Vedic multiplier modules. Urdhva tiryakbhyam Sutra is most powe ..."
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This paper presents a delay comparison of two different multipliers for unsigned data, one uses a ripple carry and the second one uses a carrylookahead adder. The 4×4 Vedic multiplier module using Urdhva Tiryakbhyam Sutra uses four 2×2 Vedic multiplier modules. Urdhva tiryakbhyam Sutra is most powerful Sutra, giving minimum delay for multiplication of all types of numbers, either small or large. Urdhva Triyagbhyam – Vedic method for multiplication which strikes a difference in the real process of multiplication itself. It causes parallel generation of intermediate products,removes unwanted multiplication steps with zeros and scaled to higher bit levels. The paper’s main focus is on the speed/delay of the multiplication operation on 4bit multipliers which are modeled using VHDL, A hardware description language. The 4×4 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 9.1 software. This multiplier is implemented on Spartan 3 FPGA device XC3S505pq208. The performance evaluation results in terms of speed and device utilization. The multiplier with a carrylookahead adder has shown a less delay over the multiplier with a ripple carry adder. The multiplier with a ripple adder uses time = 17.796 ns, while the multiplier with the carrylookahead adder uses time = 17.560 ns.