Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this paper, we consider crosstalk avoidance during global routing. We present a global routing algorithm based on a new Steiner tree formulation and the Lagrangian relaxation technique. We also give theoretical results on the complexity of the problem. 1

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

Due to the large die sizes and tight relative clock skew margins, the impact of interconnect manufacturing variations on the clock skew in today's gigahertz microprocessors can no longer be ignored. Unlike manufacturing variations in the devices, the impact of the interconnect manufacturing variations on IC timing performance cannot be captured by worst/best case corner point methods. Thus it is difficult to estimate the clock skew variability due to interconnect variations. In this paper we analyze the timing impact of several key statistically independent interconnect variations in a context-dependent manner by applying a previously reported interconnect variational order-reduction technique. The results show that the interconnect variations can cause up to 25% clock skew variability in a modern microprocessor design.

This paper addresses post-routing capacitance extraction during performance-driven layout. We first show how basic drivers in process technology (planarization and minimum metal density requirements) actually simplify the extraction problem; we do this by proposing and validating five "foundations" through detailed experiments with a 3-D field solver on representative 0:50¯m, 0:35¯m and 0:18¯m process parameters. We then present a simple yet accurate 2 1/2-D extraction methodology directly based on the foundations. This methodology has been productized and is being shipped with the Cadence Silicon Ensemble 5.0 product. We conclude that the 2 1/2-D approach has sufficient accuracy for current and near-term process generations. An extended abstract of this paper can be found in the proceedings of ACM/IEEE Design Automation Conference, Anaheim, CA, June 9-13, 1997. This work is partially supported by Cadence under the 1996 California MICRO Program. Lei He did much of this work as an in...

In this paper the fundamental electrical limits of MOSFETs are discussed and modeled to predict the scaling limits of digital bulk CMOS circuits. Limits discussed include subthreshold leakage, short channel effects (SCE), gate induced drain leakage (GIDL), gate tunneling current, time dependent dielectric breakdown (TDDB), and hot carrier effects (HCE). This paper predicts the scaling of bulk CMOS MOSFETs for high performance microprocessors to reach its limits at drawn lengths of approximately 0:08¯m. Trends in scaling interconnects are also discussed. The device limits presented are used to project the characteristics of future processor technologies and to find scaling factors for the SPICE level 3 model parameters. A SPICE device model which can be scaled to reflect a range of MOSFET technologies from drawn lengths of 0:5¯m to 0:1¯m is presented along with a scalable wire model. Key Words and Phrases: MOSFET, device scaling, interconnect scaling, subthreshold leakage, short channel...

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design specification. This paper proposes a crosstalk minimization technique based on segment rearrangement for gridded channel routing.The technique repeatedly rearranges horizontal wire segments and/or increase the number of tracks to satisfy the crosstalk constraints. With experiments, we observed that the presented technique is more effective than the track permutation technique. Keywords---coupling capacitance, crosstalk, channel routing, segment rearrangement. I. Introduction The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. The coupling capaci...

Abstract—The dynamic and short-circuit power consumption of a complementary metal–oxide–semidconductor (CMOS) gate driving an inductance–capacitance (LC) transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed-form solutions for the output voltage and shortcircuit power of a CMOS gate driving an LC transmission line are presented. A closed form solution for the short-circuit power is also presented. These solutions agree with circuit simulations within 11 % error for a wide range of transistor widths and line impedances for a 0.25-"m CMOS technology. The ratio of the short circuit to dynamic power is shown to be less than 7 % for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects becomes more significant as compared to a resistance–capacitance (RC)-dominated interconnect line. Index Terms—CMOS, dynamic, interconnect, LC, power dissipation, RC, RLC, short-circuit, transmission lines.

Measured Equation of Invariance(MEI) is a new concept in computational electromagnetics. It has been demonstrated that the MEI technique can be used to terminate the meshes very close to the object boundary and still strictly preserves the sparsity of the FD equations. Therefore, the final system matrix encountered by MEI is a sparse matrix with size similar to that of integral equation methods. However, complicated Green's function and disagreeable Sommerfeld integrals make the traditional MEI very difficult, if not impossible, to be applied to analyze multilayer and multiconductor interconnects. In this paper, we propose the Geometry Independent MEI(GIMEI) which substantially improved the original MEI method. We use GIMEI for capacitance extraction of general three-dimension VLSI interconnect. Numerical results are in good agreement with published data and those obtained by using FASTCAP [1], while GIMEI is generally an order of magnitude faster than FASTCAP and uses significant less...

The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive-capacitive interconnect lines is presented in this paper for different signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate are presented for a variety of signal activity conditions. The uncertainty of the effective load capacitance on the propagation delay due to the signal activity is also addressed. It is demonstrated that the effective load capacitance of a CMOS logic gate depends upon the intrinsic load capacitance, the coupling capacitance, the signal activity, and the size of the CMOS logic gates within a capacitively coupled system. Some design strategies are also suggested to reduce the peak noise voltage and the propagation delay caused by the interconnect coupling capacitance.

The complicated manufacturing processes dictate that process variations are unavoidable in today’s VLSI products. Unlike device variations, which can be captured by worst/best case corner points, the effects of interconnect variations are context-dependent, which makes it difficult to capture the true worst-case timing performance. This paper discusses an efficient method to explore the extreme values of performance metrics and the specific parameters that will create these extreme performances. The described approach is based on a iterative search technique which facilitates its proper search direction by calculating an explicit analytical approximation model.