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Cryptographic hardness for learning intersections of halfspaces
- J. Comput. Syst. Sci
"... We give the first representation-independent hardness results for PAC learning intersections of halfspaces, a central concept class in computational learning theory. Our hardness results are derived from two public-key cryptosystems due to Regev, which are based on the worstcase hardness of well-stu ..."
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Cited by 23 (11 self)
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We give the first representation-independent hardness results for PAC learning intersections of halfspaces, a central concept class in computational learning theory. Our hardness results are derived from two public-key cryptosystems due to Regev, which are based on the worstcase hardness of well-studied lattice problems. Specifically, we prove that a polynomialtime algorithm for PAC learning intersections of n ε halfspaces (for a constant ε> 0) in n dimensions would yield a polynomial-time solution to Õ(n 1.5)-uSVP (unique shortest vector problem). We also prove that PAC learning intersections of n ε low-weight halfspaces would yield a polynomial-time quantum solution to Õ(n 1.5)-SVP and Õ(n 1.5)-SIVP (shortest vector problem and shortest independent vector problem, respectively). Our approach also yields the first representation-independent hardness results for learning polynomialsize depth-2 neural networks and polynomial-size depth-3 arithmetic circuits. Key words: Cryptographic hardness results, intersections of halfspaces, computational learning theory, lattice-based cryptography 1
Bit-Level Analysis of an SRT Divider Circuit
- IN PROCEEDINGS OF THE 33RD DESIGN AUTOMATION CONFERENCE, PAGES 661--665, LAS VEGAS, NV
, 1995
"... It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using ..."
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Cited by 22 (0 self)
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It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we show that Intel could haveused BDDs to detect erroneous lookup table entries in the Pentium(TM) floating point divider. Going beyond verification, we show that bit-level analysis can be used to generate a correct version of the table.
Read-once Projections and Formal Circuit Verification with Binary Decision Diagrams
- Proc. STACS'96
, 1995
"... Computational complexity is concerned with the complexity of solving problems and computing functions and not with the complexity of verifying circuit designs. The importance of formal circuit verification is evident. Therefore, a framework of a complexity theory for formal circuit verification with ..."
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Cited by 4 (1 self)
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Computational complexity is concerned with the complexity of solving problems and computing functions and not with the complexity of verifying circuit designs. The importance of formal circuit verification is evident. Therefore, a framework of a complexity theory for formal circuit verification with binary decision diagrams is developed. This theory is based on read-once projections. For many problems it is determined whether and how they are related with respect to read-once projections. It is proved that multiplication can be reduced to squaring but squaring is not a read-once projection of multiplication. This perhaps surprising result is discussed. For most of the common binary decision diagram models of polynomial size complete problems with respect to read-once projections are described. But for the class of functions with polynomial-size free binary decision diagrams (read-once branching programs) no complete problem with respect to read-once projection exists. Supported by DF...
Powering requires threshold depth 3
- Inf. Process. Lett
, 2007
"... We study the circuit complexity of the powering function, defined as POWm(Z) = Z m for an n-bit integer input Z and an integer exponent m � poly(n). Let � LTd denote the class of functions computable by a depth-d polynomial-size circuit of majority gates. We give a simple proof that POWm � ∈ � LT2 ..."
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Cited by 4 (4 self)
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We study the circuit complexity of the powering function, defined as POWm(Z) = Z m for an n-bit integer input Z and an integer exponent m � poly(n). Let � LTd denote the class of functions computable by a depth-d polynomial-size circuit of majority gates. We give a simple proof that POWm � ∈ � LT2 for any m � 2. Specifically, we prove a 2 Ω(n/logn) lower bound on the size of any depth-2 majority circuit that computes POWm. This work generalizes Wegener’s earlier result that the squaring function (i.e., POWm for the special case m = 2) is not in � LT2. Our depth lower bound is optimal due to Siu and Roychowdhury’s matching upper bound: POWm ∈ � LT3. The second part of this research note presents several counterintuitive findings about the membership of arithmetic functions in the circuit classes � LT1 and � LT2. For example, we construct a function f (Z) such that f � ∈ � LT1 but 5 f ∈ � LT1. We obtain similar findings for � LT2. This apparent brittleness of � LT1 and � LT2 highlights a difficulty in proving lower bounds for arithmetic functions.
Restricted Branching Programs and Hardware Verification
, 1995
"... Recent developments in the field of digital design and hardware verification have found great use for restricted forms of branching programs. In particular, oblivious read-once branching programs (also called "OBDD's") are central to a very common technique for verifying circuits. These programs are ..."
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Cited by 3 (0 self)
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Recent developments in the field of digital design and hardware verification have found great use for restricted forms of branching programs. In particular, oblivious read-once branching programs (also called "OBDD's") are central to a very common technique for verifying circuits. These programs are useful because they are easily manipulated and compared for equivalence. However, their utility is limited because they cannot compute in polynomial size several simple functions---most notably, integer multiplication. This limitation has prompted the consideration of alternative models, usually restricted classes of branching programs, in the hope of finding one with greater computational power but also easily manipulated and tested for equivalence.
BDDs - Design, Analysis, Complexity, and Applications
- Discrete Applied Mathematics 138
, 2004
"... BDDs (binary decision diagrams) and their variants are the most frequently used representation types or data structures for boolean functions. Research on BDD variants has turned out to be one of the areas where the symbiosis between theoretical investigations in algorithm design and analysis, compl ..."
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Cited by 2 (0 self)
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BDDs (binary decision diagrams) and their variants are the most frequently used representation types or data structures for boolean functions. Research on BDD variants has turned out to be one of the areas where the symbiosis between theoretical investigations in algorithm design and analysis, complexity theory, and applications has led to progress in theory and in applications. Here the different roots of the interest in BDDs are described, the main BDD variants and their algorithmic properties are presented, the representation size of selected functions is investigated, lower bound techniques are discussed and applications to algorithmic graph problems and hardware verification problems are presented.
General Purpose Computation with Neural Networks: A Survey of Complexity Theoretic Results
, 2003
"... We survey and summarize the existing literature on the computational aspects of neural network models, by presenting a detailed taxonomy of the various models according to their complexity theoretic characteristics. The criteria of classi cation include e.g. the architecture of the network (fee ..."
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Cited by 2 (0 self)
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We survey and summarize the existing literature on the computational aspects of neural network models, by presenting a detailed taxonomy of the various models according to their complexity theoretic characteristics. The criteria of classi cation include e.g. the architecture of the network (feedforward vs. recurrent), time model (discrete vs. continuous), state type (binary vs. analog), weight constraints (symmetric vs. asymmetric), network size ( nite nets vs. in - nite families), computation type (deterministic vs. probabilistic), etc.
Cryptographic hardness results for learning intersections of halfspaces
, 2006
"... We give the first representation-independent hardness results for PAC learning intersections of halfspaces, a central concept class in computational learning theory. Our hardness results are derived from two public-key cryptosystems due to Regev, which are based on the worstcase hardness of well-stu ..."
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Cited by 1 (0 self)
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We give the first representation-independent hardness results for PAC learning intersections of halfspaces, a central concept class in computational learning theory. Our hardness results are derived from two public-key cryptosystems due to Regev, which are based on the worstcase hardness of well-studied lattice problems. Specifically, we prove that a polynomial-time algorithm for PAC learning intersections of n ǫ halfspaces (for a constant ǫ> 0) in n dimensions would yield a polynomial-time solution to Õ(n1.5)-uSVP (unique shortest vector problem). We also prove that PAC learning intersections of n ǫ low-weight halfspaces would yield a polynomialtime quantum solution to Õ(n1.5)-SVP and Õ(n1.5)-SIVP (shortest vector problem and shortest independent vector problem, respectively). By making stronger assumptions about the hardness of uSVP, SVP, and SIVP, we show that there is no polynomial-time algorithm for learning intersections of log c n halfspaces in n dimensions, for c> 0 sufficiently large. Our approach also yields the first representation-independent hardness results for learning polynomial-size depth-2 neural networks and polynomial-size depth-3 arithmetic circuits. 1
The Computational Theory of Neural Networks
, 2000
"... In the present paper a detailed taxonomy of neural network models with various restrictions is presented with respect to their computational properties. The criteria of classification include e.g. feedforward and recurrent architectures, discrete and continuous time, binary and analog states, symmet ..."
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In the present paper a detailed taxonomy of neural network models with various restrictions is presented with respect to their computational properties. The criteria of classification include e.g. feedforward and recurrent architectures, discrete and continuous time, binary and analog states, symmetric and asymmetric weights, finite size and infinite families of networks, deterministic and probabilistic models, etc. The underlying results concerning the computational power of perceptron, RBF, winner-take-all, and spiking neural networks are briey surveyed and completed by relevant references.

