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BURG  Fast Optimal Instruction Selection and Tree Parsing
 SIGPLAN Notices
, 1991
"... This document describes only that fraction of the BURS model that is required to use Burg. Readers interested in more detail might start with Reference [BDB90]. Other relevant documents include References [Kro75, HO82, HC86, Cha87, PLG88, PL87, BMW87, Hen89, FH91, Pro91] ..."
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Cited by 40 (2 self)
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This document describes only that fraction of the BURS model that is required to use Burg. Readers interested in more detail might start with Reference [BDB90]. Other relevant documents include References [Kro75, HO82, HC86, Cha87, PLG88, PL87, BMW87, Hen89, FH91, Pro91]
Code generation based on formal BURS theory and heuristic search
 Acta Informatica
, 1997
"... BURS theory provides a powerful mechanism to efficiently generate pattern matches in a given expression tree. BURS, which stands for bottomup rewrite system, is based on term rewrite systems, to which costs are added. We formalise the
underlying theory, and derive an algorithm that computes all pat ..."
Abstract

Cited by 17 (2 self)
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BURS theory provides a powerful mechanism to efficiently generate pattern matches in a given expression tree. BURS, which stands for bottomup rewrite system, is based on term rewrite systems, to which costs are added. We formalise the
underlying theory, and derive an algorithm that computes all pattern matches. This algorithm terminates if the term rewrite system is finite. We couple this algorithm with
the wellknown search algorithm A* that carries out pattern selection. The search algorithm is directed by a cost heuristic that estimates the minimum cost of code that
has yet to be generated. The advantage of using a search algorithm is that we need to compute only those costs that may be part of an optimal rewrite sequence (and not the costs of all possible rewrite sequences as in dynamic programming). A system that implements the algorithms presented in this work has been built.
Hardcoding Bottomup Code Generation Tables to Save Time and Space
, 1991
"... This paper describes a program that compiles BURS tables into a combination of hard code and data. Hardcoding exposed important opportunities for compression that were previously hidden in the tables, so the hardcoded code generators are not just faster but also significantly smaller than their pr ..."
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Cited by 12 (4 self)
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This paper describes a program that compiles BURS tables into a combination of hard code and data. Hardcoding exposed important opportunities for compression that were previously hidden in the tables, so the hardcoded code generators are not just faster but also significantly smaller than their predecessors. A VAX code generator takes 21.4Kbytes and identifies optimal assembly code in about 50 VAX instructions per node
PhaseCoupled Mapping of Data Flow Graphs to Irregular Data Paths
 Embedded Systems
, 1999
"... . Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable ..."
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Cited by 10 (2 self)
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. Many software compilers for embedded processors produce machine code of insufficient quality. Since for most applications software must meet tight code speed and size constraints, embedded software is still largely developed in assembly language. In order to eliminate this bottleneck and to enable the use of highlevel language compilers also for embedded software, new code generation and optimization techniques are required. This paper describes a novel code generation technique for embedded processors with irregular data path architectures, such as typically found in fixedpoint DSPs.The proposed code generation technique maps data flow graph representation of a program into highly efficient machine code for a target processor modeled by instruction set behavior. High code quality is ensured by tight coupling of different code generation phases. In contrast to earlier works, mainly based on heuristics, our approach is constraintbased. An initial set of constraints on code generati...
Code Generation Techniques
 In INFOCOM (1
, 1992
"... Optimal instruction scheduling and register allocation are NPcomplete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayedload architectures to expression trees we are able to find optimal schedules quickly. This thesis ..."
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Cited by 5 (0 self)
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Optimal instruction scheduling and register allocation are NPcomplete problems that require heuristic solutions. By restricting the problem of register allocation and instruction scheduling for delayedload architectures to expression trees we are able to find optimal schedules quickly. This thesis presents a fast, optimal code scheduling algorithm for processors with a delayed load of 1 instruction cycle. The algorithm minimizes both execution time and register use and runs in time proportional to the size of the expression tree. In addition, the algorithm is simple
Code Generation = A* + BURS
 Compiler Construction
, 1996
"... A system called BURS that is based on term rewrite systems and a search algorithm A* are combined to produce a code generator that generates optimal code. The theory underlying BURS is redeveloped, formalised and explained in this work. The search algorithm uses a cost heuristic that is derived fro ..."
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Cited by 1 (1 self)
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A system called BURS that is based on term rewrite systems and a search algorithm A* are combined to produce a code generator that generates optimal code. The theory underlying BURS is redeveloped, formalised and explained in this work. The search algorithm uses a cost heuristic that is derived from the term rewrite system to direct the search. The advantage of using a search algorithm is that we need to compute only those costs that may be part of an optimal rewrite sequence.
Optimal regular tree pattern matching using pushdown automata
, 1998
"... Abstract. We propose a construction that augments the precomputation step of a regular tree pattern matching algorithm to include cost analysis. The matching device generated is a pushdown automaton in contrast with the conventionallygenerated tree pattern matching automaton. Our technique can handl ..."
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Cited by 1 (1 self)
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Abstract. We propose a construction that augments the precomputation step of a regular tree pattern matching algorithm to include cost analysis. The matching device generated is a pushdown automaton in contrast with the conventionallygenerated tree pattern matching automaton. Our technique can handle a larger class of cost augmented regular tree grammars than can be preprocessed byconventional methods, and has been tested on some input problem instances representing instruction sets for processors. 1