Abstract. Instruction selection for embedded processors is a challenging problem. Embedded system architectures feature highly irregular instruction sets and complex data paths. Traditional code generation techniques have difficulties to fully utilize the features of such architectures and typically result in inefficient code. In this paper we describe an instruction selection technique that uses static single assignment graphs (SSA-graphs) as underlying data structure for selection. Patterns defined as graph grammar guide the instruction selection to find (nearly) optimal results. We present an approach which maps the pattern matching problem to a partitioned boolean quadratic optimization problem (PBQP). A linear PBQP solver computes optimal solutions for almost all nodes of a SSA-graph. We have implemented our approach in a production DSP compiler. Our experiments show that our approach achieves significant better results compared to classical tree matching. 1

With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific instruction-set processors (ASIPs) are used to fine-tune hardware platforms to the intended application, demanding the availability of retargetable components throughout the whole tool chain. A very promising approach is to model the target architecture using a dedicated description language that is rich enough to generate hardware components and the required tool chain, e.g., assembler, linker, simulator, and compiler. In this work we present a new structural architecture description language (ADL) that is used to derive the architecture dependent components of a compiler backend — most notably an instruction selector based on tree pattern matching. We combine our backend with gcc, thereby opening up the way for a large number of readily available high level optimizations. Experimental results show that the automatically derived code generator is competitive in comparison to a handcrafted compiler backend.

As regards competitiveness, flexibility to change from one target platform to another is decisive for application developers, especially in the area of embedded systems. The Architecture Neutral Distribution Format (ANDF), developed and evaluated within OMI (Open Microprocessor Systems Initiative) has turned out to be a key technology to improve this flexibility. The basic idea is to break compilers into front-ends (for specific languages) and back-ends (for specific microprocessors) where both pieces easily could be replaced by a "plug-and-play" compatible component.

This tutorial responds to the rapidly increasing use of cores in general and of processor cores in particular for implementing systems-on-a-chip. In the first part of this text, we will provide a brief introduction to various cores. Applications can be found in most segments of the embedded systems market. These applications demand for extreme efficiency, and in particular for efficient processorarchitecturesand for efficient embedded software. In the second part of this text, we will show that current compilers do not provide the required efficiency and we will give an overview over new compiler optimization techniques,which aim at making assembly language programming for embedded software obsolete. Thesenew techniquestake advantageof the special characteristics of embedded software and embedded architectures. Due to efficiency considerations, processorarchitecturesoptimized for application domains or even for particular applications are of interest. This results in a large number of ...

A system called BURS that is based on term rewrite systems and a search algorithm A* are combined to produce a code generator that generates optimal code. The theory underlying BURS is re-developed, formalised and explained in this work. The search algorithm uses a cost heuristic that is derived from the term rewrite system to direct the search. The advantage of using a search algorithm is that we need to compute only those costs that may be part of an optimal rewrite sequence.

Abstract. We propose a construction that augments the precomputation step of a regular tree pattern matching algorithm to include cost analysis. The matching device generated is a pushdown automaton in contrast with the conventionallygenerated tree pattern matching automaton. Our technique can handle a larger class of cost augmented regular tree grammars than can be preprocessed byconventional methods, and has been tested on some input problem instances representing instruction sets for processors. 1

We propose a new technique for constructing code-generator generators, which combines the advantages of the Graham-Glanville parsing technique and the bottom-up tree parsing approach. Machine descriptions are similar to Yacc specifications. The construction effectively generates a pushdown automaton as the matching device. This device is able to handle ambiguous grammars, and can be used to generate locally optimal code without the use of heuristics. Cost computations are performed at preprocessing time. The class of regular tree grammars augmented with costs that can be handled by our system properly includes those that can be handled by bottom-up systems based on finite-state tree parsing automata. Parsing time is linear in the size of the subject tree. We have tested the system on specifications for some systems and report table sizes.

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