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37
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 115 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
A new class of iterative Steiner tree heuristics with good performance
 IEEE TRANS. COMPUTERAIDED DESIGN
, 1992
"... ... problem is very important for such aspects of physical layout as global routing and wiring estimation. Virtually all previous heuristics for computing rectilinear Steiner trees begin with a minimum spanning tree (MST) topology and rearrange edges to induce Steiner points. This paper gives a more ..."
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Cited by 96 (32 self)
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... problem is very important for such aspects of physical layout as global routing and wiring estimation. Virtually all previous heuristics for computing rectilinear Steiner trees begin with a minimum spanning tree (MST) topology and rearrange edges to induce Steiner points. This paper gives a more direct approach which makes a significant departure from such spanning treebased strategies: we iteratively find optimal Steiner points to be added to the layout. Our method not only gives improved averagecase performance, but also escapes the worstcase examples of existing approaches. We show that the performance ratio of our method can never be as bad as 3/2, and is in fact bounded by 4/3 on the entire class of instances where the c(MST)/c(MRST) cost ratio is exactly 3/2. Sophisticated computational geometry techniques allow efficient and practical implementation, and the method is naturally suited to technological regimes where, e.g., via costs can be high and the number of Steiner points should be limited. Extensive performance results show a 2 % to 3 % wire length reduction over the best previous heuristics. We describe a number of variants and extensions, and suggest directions for further research.
NearOptimal Critical Sink Routing Tree Constructions
, 1995
"... We present criticalsink routing tree (CSRT) constructions which exploit available criticalpath information to yield highperformance routing trees. Our CSSteiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at id ..."
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Cited by 55 (13 self)
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We present criticalsink routing tree (CSRT) constructions which exploit available criticalpath information to yield highperformance routing trees. Our CSSteiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67%) over minimum Steiner routings in terms of delays to identified critical sinks. ERTs also serve as generic highperformance routing trees when no critical sink is specified: for 8sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the mini...
Closing the Gap: NearOptimal Steiner Trees in Polynomial Time
 IEEE Trans. ComputerAided Design
, 1994
"... The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In ..."
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Cited by 43 (13 self)
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The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves nearlinear speedup on multiple processors. Several performanceimproving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multilayer routing. Motivated by the goal of reducing the running times of our algorith...
HighPerformance Routing Trees With Identified Critical Sinks
, 1992
"... We present two criticalsink routing tree (CSRT) constructions which exploit criticalpath information that becomes available during timingdriven layout. Our CSSteiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significa ..."
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Cited by 38 (13 self)
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We present two criticalsink routing tree (CSRT) constructions which exploit criticalpath information that becomes available during timingdriven layout. Our CSSteiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significantly lower criticalsink delays compared with existing performancedriven methods. We also propose a new class of Elmore routing tree (ERT) constructions, which iteratively add tree edges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identified critical sinks by up to 69 % over minimum Steiner routings. ERTs also improve performance over such recent methods as [1] [6] when no critical sinks are specified.
PrimDijkstra Tradeoffs for Improved PerformanceDriven Routing Tree Design
, 1995
"... Analysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining ..."
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Cited by 33 (4 self)
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Analysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining respectively optimal algorithms due to Prim and Dijkstra. Previous "shallowlight" techniques [2, 3, 8, 13] are both less direct and less effective: in practice, our methods achieve uniformly superior costradius tradeoffs. Detailed timing simulations for a range of IC and MCM interconnect technologies show that our wirelength savings yield reduced signal delays when compared to shallowlight or standard minimum spanning tree and Steiner tree routing.
Efficient steiner tree construction based on spanning graphs
 IEEE Transactions ComputerAided Design
, 2004
"... Abstract—The Steiner Minimal Tree (SMT) problem is a very important problem in very large scale integrated computeraided design. Given points on a plane, an SMT connects these points through some extra points (called Steiner points) to achieve a minimal total length. Even though there exist many he ..."
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Cited by 30 (5 self)
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Abstract—The Steiner Minimal Tree (SMT) problem is a very important problem in very large scale integrated computeraided design. Given points on a plane, an SMT connects these points through some extra points (called Steiner points) to achieve a minimal total length. Even though there exist many heuristic algorithms for this problem, they have either poor performances or expensive running time. This paper records an implementation of an efficient SMT algorithm that has a worst case running time of ( log) and a performance close to that of the Iterated 1Steiner algorithm. The algorithm efficiently combines Borah et al.’s edge substitute concept with Zhou et al.’s spanning graph. Extensive experimental studies are conducted to compare it with other programs. Index Terms—Graph algorithms, routing, Steiner tree. I.
LowDegree Minimum Spanning Trees
 Discrete Comput. Geom
, 1999
"... Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where ..."
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Cited by 24 (1 self)
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Motivated by practical VLSI routing applications, we study the maximum vertex degree of a minimum spanning tree (MST). We prove that under the Lp norm, the maximum vertex degree over all MSTs is equal to the Hadwiger number of the corresponding unit ball; we show an even tighter bound for MSTs where the maximum degree is minimized. We give the bestknown bounds for the maximum MST degree for arbitrary Lp metrics in all dimensions, with a focus on the rectilinear metric in two and three dimensions. We show that for any finite set of points in the rectilinear plane there exists an MST with maximum degree of at most 4, and for threedimensional rectilinear space the maximum possible degree of a minimumdegree MST is either 13 or 14. 1 Introduction Minimum spanning tree (MST) construction is a classic optimization problem for which several efficient algorithms are known [9] [15] [19]. Solutions of many other problems hinge on the construction of an MST as an intermediary step [4], with th...
A New Heuristic for Rectilinear Steiner Trees
 In Proc. IEEE Int. Conf. on CAD
"... The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NPhard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST he ..."
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Cited by 19 (2 self)
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The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NPhard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1Steiner (BI1S) heuristic of Kahng and Robins. In a recent development, exact RST algorithms have witnessed spectacular progress: The new release of the GeoSteiner code of Warme, Winter, and Zachariasen has average running time comparable to that of the fastest available BI1S implementation, due to Robins. We are thus faced with the paradoxical situation that an exact algorithm for an NPhard problem is competitive in speed with a stateoftheart heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3=2 approximation algorithm of Rajagopalan and Vazirani for the metric Steiner tree problem on ...
On the BoundedSkew Clock and Steiner Routing Problems
, 1995
"... We study the minimumcost boundedskewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology ExtendedDME (ExDME) extends th ..."
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Cited by 15 (4 self)
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We study the minimumcost boundedskewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. We propose three tradeoff heuristics. (1) For a fixed topology ExtendedDME (ExDME) extends the DME algorithm for exact zeroskew trees via the concept of a merging region. (2) For arbitrary topology and arbitrary embedding, Extended GreedyDME (ExGDME) very closely matches the best known heuristics for the zeroskew case,and for the infiniteskew case (i.e.,the Steiner minimal tree problem). (3) For arbitrary topology and singlelayer (planar) embedding, the Extended PlanarDME (ExPDME) algorithm exactly matches the best known heuristic for zeroskew planar routing, and closely approaches the best known performance for the infiniteskewcase. Our work provides unifications of the clock routing and Steiner tree heuristic literatures and gives smooth costskew tradeoff that enable good engineering solutions.