This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSPs, ASICS, and FPGA subsystems. Thus, it is particularly well suited to the evolving trend towards heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation [36] that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of additional synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus the net synchronization cost is reduc...

Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive environment for guiding the exploration process. A prototype targeting behavioral-level optimization for datapath-intensive ASIC implementations has been developed. The key to the approach is encapsulated knowledge about the various optimizations and a set of techniques to automatically extract the "essence" of a design description. At each stage in the exploration process, the system suggests and ranks potential optimizations, both in terms of immediate and longer-term impact. It also provides evaluations of the design and of the likely affects each optimization will have on metrics like power and performance. In the new approach, the designer is responsible for making the actual optimization selections. However, using the provided guidance, designers can make decisions in a more informed manner, and therefore can explore the design solution space more effectively. The effectiveness of the approach is demonstrated on a number of designs.

Application studies in the domain of image and video processing systems indicate that up to 80% of the power and area cost in customized architectures for such data-dominant processing is due to storage and transfers for multi-dimensional (M-D) data. This paper has two main contributions. First, to reduce this dominant cost, we propose a formalized methodology of data-flow transformations which address the system-level storage organization. Secondly, we will demonstrate the usefulness of the stages in this novel approach based on realistic test-vehicles, i.e. crucial modules in a complex H.263 video decoder system for teleconferencing. 1. MOTIVATION AND CONTEXT Advanced video and image processing algorithms are very data-dominant. A hardware realization of such applications has to be power efficient in order to reduce the size of the chip packages where it is embedded, or the battery if it would be used in a mobile application. It is well-known by now that any future complex chip re...

This paper introduces a technique, called resynchronization, for reducing synchronization overhead in multiprocessor implementations of digital signal processing (DSP) systems. The technique applies to arbitrary collections of dedicated, programmable or configurable processors, such as combinations of programmable DSP's, ASICS, and FPGA subsystems. Thus, it is particularly well-suited to the evolving trend toward heterogeneous single-chip multiprocessors in DSP systems. Resynchronization exploits the well-known observation [43] that in a given multiprocessor implementation, certain synchronization operations may be redundant in the sense that their associated sequencing requirements are ensured by other synchronizations in the system. The goal of resynchronization is to introduce new synchronizations in such a way that the number of original synchronizations that become redundant exceeds the number of new synchronizations that are added, and thus, the net synchronization cost is reduced.

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ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms. 1 Introduction Phenomenal advances in silicon micro-chip technology have brought about a paradigm shift in the realization of future systems-on-a-chip. Embedded systems are now being increasingly considered to form part of such systems. Re-targettable, domain specif...

Algebraic properties such as associativity or distributivity allow the manipulation of a set of mathematically equivalent expressions. However, as shown in this paper, the cost of evaluating such expressions on a computer is not constant within this domain. We suggest the use of algebraic transformations to improve the performance of computationally intensive applications on modern computer architectures. We claim that taking into account instruction-level parallelism and the new capabilities of processors when applying these transformations leads to large run-time improvements. Due to a combinatorial explosion, associativecommutative pattern-matching techniques cannot systematically be used in this context. Thus, we introduce two performance enhancing algorithms providing factorization and multiply-add extraction heuristics and choice criteria based on a simple cost model. This paper describes our approach and a first implementation. Experiments on real code, including an excerpt from...

Behavioral-Level Guidance Using Property-Based Design Lisa Marie Guerra Doctor of Philosophy in Engineering --- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair The growing importance of optimization, short time to market windows, and exponentially growing design complexity are just a few of the factors shaping the state-of-the-art synthesis process. In particular, optimization at the early stages of design is crucial --- at the system and behavioral levels, orders of magnitude performance improvement in key design metrics such as throughput, power, and area can be attained. This requires, however, strategic and coordinated application of design techniques best suited for a target design. The problem, however, is the number of options currently available is overwhelming, and as a result, design exploration is often conducted in a qualitative, ad-hoc manner.

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This paper considers the rate optimal VLSI design of a recursive data #ow graph #DFG#. Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts bu#er registers to allowoverlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if exists, than overlapped schedules. 1 Introduction A data #ow graph #DFG# is a useful speci#cation method in many application #elds including digital signal processing, parallel programming, high level synthesis and so on. Now that DFG plays a signi#cant role as an algorithm speci#cation method in high level system design, it becomes more importanthow to implement VLSI from a given DFG. Currently many existing tools support the synthesis of VLSI from DFGinvarious ways #1##2##3#. High level DFG transformation prior to VLSI implementation can play an important role in increasing the ...