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25
Scaling OptoelectronicVLSI Circuits into the 21st Century: A Technology Roadmap
 IEEE J. Selected Topics in Quantum Electronics
, 1996
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Categories, Allegories and Circuit Design
 In Ninth Annual IEEE Symposium on Logic in Computer Science
, 1994
"... Relational languages such as Ruby are used to derive hardware circuits from abstract specifications of their behaviour. Much reasoning is done informally in Ruby using pictorial representations of relational terms. We formalise this use of pictures in circuit design. We show that pictures naturally ..."
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Cited by 19 (1 self)
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Relational languages such as Ruby are used to derive hardware circuits from abstract specifications of their behaviour. Much reasoning is done informally in Ruby using pictorial representations of relational terms. We formalise this use of pictures in circuit design. We show that pictures naturally form a unitary pretabular allegory. Homomorphisms of pictures correspond to adding new wires or circuit components. Two pictures are mutually homomorphic if and only if they represent equal allegorical terms. We prove soundness and completeness results which guarantee that deriving circuits using pictures does not lead to errors. We illustrate the use of pictures by deriving the ripple adder implementation from a high level, behavioural specification. 1: Introduction Hardware circuit design involves translating abstract specifications of programs into efficient circuits which compute those programs. Pictures are widely used as an informal means of translating a specification into an imple...
Allegories of Circuits
 Proc. Logical Foundations of Computer Science
, 1994
"... This paper presents three paradigms for circuit design, and investigates the relationships between them. These paradigms are syntactic (based on Freyd and Scedrov's unitary pretabular allegories (upas)), pictorial (based on the net list model of circuit connectivity), and relational (based on ..."
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Cited by 13 (0 self)
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This paper presents three paradigms for circuit design, and investigates the relationships between them. These paradigms are syntactic (based on Freyd and Scedrov's unitary pretabular allegories (upas)), pictorial (based on the net list model of circuit connectivity), and relational (based on Sheeran's relational model of circuit design Ruby). We show that net lists over a given signature \Sigma constitute the free upa on \Sigma. Our proof demonstrates that nets and upas are equally expressive, and that nets provide a normal form for both upas and pictures. We use Freyd and Scedrov's representation theorem for upas to show that our relational interpretations constitute a sound and complete class of models for the upa axioms. Thus we can reason about circuits using either the upa axioms, pictures or relations. By considering garbage collection, we show that there is no faithful representation of nets in Rel: we conjecture that a semantics for nets which takes garbage collection into ac...
FASY: A fuzzylogic based tool for analog synthesis
 IEEE Transactions on ComputerAided Design of Integrated Circuits
, 1996
"... A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost functio ..."
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A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies. 1 1
Encoding A Priori Information In Feedforward Networks
, 1991
"... Theoretical results and practical experience indicate that feedforward networks are very good at approximating a wide class of functional relationships. Training networks to approximate functions takes place by using exemplars to find interconnect weights that maximize some goodness of fit criterion ..."
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Cited by 6 (2 self)
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Theoretical results and practical experience indicate that feedforward networks are very good at approximating a wide class of functional relationships. Training networks to approximate functions takes place by using exemplars to find interconnect weights that maximize some goodness of fit criterion. Given finite data sets it can be important in the training process to take advantage of any a priori information regarding the underlying functional relationship to improve the approximation and the ability of the network to generalize. This paper describes methods for incorporating a priori information of this type into feedforward networks. Two general approaches, one based upon architectural constraints and a second upon connection weight constraints form the basis of the methods presented. These two approaches can be used either alone or in combination to help solve specific training problems. Several examples covering a variety of types of a priori information, including information a...
Modeling of Power Supply Noise in Large Chips Using the Finite Difference Time Domain Method
, 2002
"... Abstract—In this paper, a multilayered onchip power distribution network consisting of two million passive elements has been modeled using the finitedifference timedomain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating ..."
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Abstract—In this paper, a multilayered onchip power distribution network consisting of two million passive elements has been modeled using the finitedifference timedomain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an Htree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately. Index Terms—Chip–package interaction, circuit finitedifference timedomain (FDTD), decoupling capacitor, large chips, onchip power distribution, power supply noise, wafer level package. I.
Parallel Logic Simulation of Digital Circuits
, 1998
"... Parallel discrete event simulation (PDES) is efficient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiment ..."
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Parallel discrete event simulation (PDES) is efficient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments were performed to demonstrate that the two proposed techniques together provide significant reduction in parallel simulation time. Unlike most other partitioning algorithms, the proposed partitioning algorithm preserves circuit concurrency by assigning circuit gates that can be evaluated at about the same time to different processors. As a result, the concurrency preserving partitioning (CPP) algorithm can provide instantaneous load balancing, instead of only aggregated load balancing, throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. In addition, a new concurrency metric is proposed to evaluate partitioning algorithms before the execution of parallel simulations. Even though PDES can reduce the logic simulation time for large circuits considerably, it generates more events than necessary for certain high activity circuits and produces inconsistent speedup over different circuits. The proposed Event Lookahead Time Warp (ETW) algorithm can look ahead and combine and execute multiple events at each gate optimistically so that the probability of unnecessary events can be reduced. As a result, it can reduce rollback cost, obtain better load balance, and achieve more consistent execution times and reasonable speedups.
Cascode Circuits for Switched Current Copiers
"... � � � — Various cascode circuits are investigated with regard to their suitability for switched current copier applications. Generalized circuit representations are introduced and different cascode circuits are compared and discussed. A method called “reference voltage and current tracking ” for d ..."
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� � � — Various cascode circuits are investigated with regard to their suitability for switched current copier applications. Generalized circuit representations are introduced and different cascode circuits are compared and discussed. A method called “reference voltage and current tracking ” for dynamic output range improvement is proposed. An improved regulated cascode circuit with extended dynamic output range is presented. The use of cascode circuits in switched current copiers and the dynamic output ranges of these circuits are discussed and the corresponding saturation operating areas are compared. I.
Analog VLSI for Neural Networks
 in Handbook of Brain Theory and Neural Networks, M. Arbib Ed
, 1995
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CASCODE CIRCUITS FOR LOWVOLTAGE AND LOWCURRENT APPLICATIONS
"... Different cascode circuits are investigated with regard to their suitability for lowvoltage and lowcurrent circuits.A generalized circuit representation is introduced and different cascode circuits are discussed with respect to their smallsignal parameters as well as their associated dynamic outp ..."
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Cited by 1 (1 self)
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Different cascode circuits are investigated with regard to their suitability for lowvoltage and lowcurrent circuits.A generalized circuit representation is introduced and different cascode circuits are discussed with respect to their smallsignal parameters as well as their associated dynamic output ranges.The output voltage ranges for saturation operation of the different cascode circuits are derived and the saturation operating areas are compared.A method called reference voltage and current tracking for dynamic output range improvement of cascode circuits with reference voltage or current is described.An improved regulated cascode circuit with extended dynamic output range using input tracking and level shifting technique is proposed. 1.