Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

Relational languages such as Ruby are used to derive hardware circuits from abstract specifications of their behaviour. Much reasoning is done informally in Ruby using pictorial representations of relational terms. We formalise this use of pictures in circuit design. We show that pictures naturally form a unitary pretabular allegory. Homomorphisms of pictures correspond to adding new wires or circuit components. Two pictures are mutually homomorphic if and only if they represent equal allegorical terms. We prove soundness and completeness results which guarantee that deriving circuits using pictures does not lead to errors. We illustrate the use of pictures by deriving the ripple adder implementation from a high level, behavioural specification. 1: Introduction Hardware circuit design involves translating abstract specifications of programs into efficient circuits which compute those programs. Pictures are widely used as an informal means of translating a specification into an imple...

This paper presents three paradigms for circuit design, and investigates the relationships between them. These paradigms are syntactic (based on Freyd and Scedrov's unitary pre-tabular allegories (upas)), pictorial (based on the net list model of circuit connectivity), and relational (based on Sheeran's relational model of circuit design Ruby). We show that net lists over a given signature \Sigma constitute the free upa on \Sigma. Our proof demonstrates that nets and upas are equally expressive, and that nets provide a normal form for both upas and pictures. We use Freyd and Scedrov's representation theorem for upas to show that our relational interpretations constitute a sound and complete class of models for the upa axioms. Thus we can reason about circuits using either the upa axioms, pictures or relations. By considering garbage collection, we show that there is no faithful representation of nets in Rel: we conjecture that a semantics for nets which takes garbage collection into ac...

A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies. 1 1

Theoretical results and practical experience indicate that feedforward networks are very good at approximating a wide class of functional relationships. Training networks to approximate functions takes place by using exemplars to find interconnect weights that maximize some goodness of fit criterion. Given finite data sets it can be important in the training process to take advantage of any a priori information regarding the underlying functional relationship to improve the approximation and the ability of the network to generalize. This paper describes methods for incorporating a priori information of this type into feedforward networks. Two general approaches, one based upon architectural constraints and a second upon connection weight constraints form the basis of the methods presented. These two approaches can be used either alone or in combination to help solve specific training problems. Several examples covering a variety of types of a priori information, including information a...

Parallel discrete event simulation (PDES) is efficient in simulating a large digital circuit. In this dissertation, two techniques are proposed to improve the performance of PDES in logic simulation. One is a partitioning algorithm and the other is a hybrid parallel simulation protocol. Experiments were performed to demonstrate that the two proposed techniques together provide significant reduction in parallel simulation time. Unlike most other partitioning algorithms, the proposed partitioning algorithm preserves circuit concurrency by assigning circuit gates that can be evaluated at about the same time to different processors. As a result, the concurrency preserving partitioning (CPP) algorithm can provide instantaneous load balancing, instead of only aggregated load balancing, throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. In addition, a new concurrency metric is proposed to evaluate partitioning algorithms before the execution of parallel simulations. Even though PDES can reduce the logic simulation time for large circuits considerably, it generates more events than necessary for certain high activity circuits and produces inconsistent speedup over different circuits. The proposed Event Lookahead Time Warp (ETW) algorithm can look ahead and combine and execute multiple events at each gate optimistically so that the probability of unnecessary events can be reduced. As a result, it can reduce rollback cost, obtain better load balance, and achieve more consistent execution times and reasonable speedups.

Introduction Scaling of VLSI technology has been dramatically increasing microelectronic device densities and speeds. However, the interconnection technology between these devices does not advance proportionally. Limited available interconnect materials compatible with VLSI and packaging technologies, increased wire resistance as a result of smaller feature size, residual wire capacitance due to fringing fields and fields between interconnect wires are among the factors that prohibit drastic improvement of the electrical interconnect performance. As a result, the overall performance of VLSI systems become increasingly dominated by the performance of long interconnects. To overcome this limitation, free-space optical interconnects have been suggested, where long electrical interconnects are replaced by an optical link consisting of a light transmitter, a photodetector, and interconnection optics between them 1,2,3,4,5,6,7,8 . This scheme, although devoid of el

Introduction One of the most promising strategies for implementing neural networks is through the use of electronic analog VLSI (very large scale integration) circuits. An analog circuit is one that processes a continuum of real-valued signals of continuous time, in contrast to a digital circuit which processes integer-valued (most often binary) signals in discretized time. VLSI refers to an integrated circuit design and manufacturing technology whereby hundreds of thousands to millions of active components (most often transistors) are placed on a chip on the order of 100 mm in area and 0.5 mm thick. Because Artificial Neural Networks (ANNs) attempt to behave similarly to the brain with its millions of neurons, VLSI is the most appropriate presently available technology for their hardware implementations. Furthermore, both VLSI circuits and biological neurons are of the same class, that is, fundamentally analog. Although during the 1980s digital ANNs held most interest, the first

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable.

This work reports the development of an Application Specific Integrated Circuit (ASIC) implemented in Sea-of-Gates, suitable for digital signal processing applications. A 10th order digital filter with programmable coefficients was designed. The processing of audio frequency signals can be performed in real-time. This circuit was designed as part of the PROTEM-CC/PROCIMS project, using 1.0m CMOS technology. 1.