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Optimal Design of a CMOS OpAmp via Geometric Programming
"... We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifi ..."
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Cited by 85 (9 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs, or globally optimal tradeoffs among competing performance measures such as power, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS amplifiers, directly from specifications. In this paper we apply this method to a specific, widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
Design of mixedsignal systemsonachip
 IEEE Trans. Comput. Aided Design Integr. Circuits Syst
, 2000
"... Abstract—The electronics industry is increasingly focused on the consumer marketplace, which requires lowcost highvolume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single ..."
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Cited by 23 (2 self)
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Abstract—The electronics industry is increasingly focused on the consumer marketplace, which requires lowcost highvolume products to be developed very rapidly. This, combined with advances in deep submicrometer technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixedsignal (MS) systemsonchip presents enormous challenges both to the designers of the chips and to the developers of the computeradided design (CAD) systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large singlechip MS systems and how CAD systems are expected to develop to overcome these issues. Index Terms—Design automation, design methodology, hardware design languages, integrated circuit layout, integrated circuit modeling, mixed analogdigital integrated circuits, simulation, testing. I.
FASY: A fuzzylogic based tool for analog synthesis
 IEEE Transactions on ComputerAided Design of Integrated Circuits
, 1996
"... A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost functio ..."
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Cited by 12 (0 self)
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A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies. 1 1
Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach
"... In this paper, we present a method for optimizing and automating the components and transistor sizing for CMOS operational amplifiers (opamps). The optimization approaches used for the synthesis of analog circuits are found to be very much rigid in terms of capturing human intentions. In this work, ..."
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Cited by 1 (0 self)
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In this paper, we present a method for optimizing and automating the components and transistor sizing for CMOS operational amplifiers (opamps). The optimization approaches used for the synthesis of analog circuits are found to be very much rigid in terms of capturing human intentions. In this work, we have observed that with the use of fuzzy membership functions, human intentions for expressing wide variety of requirements, e.g., minimize power, maximize gain, etc., which are often conflicting in nature, can be captured effectively in order to formulate the objective function. For each of the performance specifications of a given topology, a membership function is assigned to measure the degree of fulfillment of the objectives and the constraints. A number of objectives are optimized simultaneously by assigning weights to each of them representing their relative importance, and then by clustering together to form the objective function that is solved by an optimization algorithm. We have considered the channel length modulation parameter (λ) for the computation of DC bias point and small signal parameters. The design results obtained from our optimization algorithm showed an excellent match with those obtained from SPICE simulation for a number of opamp topologies. 1.
Sizing of Analog Cells by Means of a Tabu Search Approach
"... Although many design tools have been developed for digital design, analog design tools are only just being introduced. This paper presents a new optimization method for automatically sizing the circuit topology of analog cells. This method minimizes a cost function, which depends on a set of designe ..."
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Although many design tools have been developed for digital design, analog design tools are only just being introduced. This paper presents a new optimization method for automatically sizing the circuit topology of analog cells. This method minimizes a cost function, which depends on a set of designer specifications. It employs the tabu search heuristic to avoid being trapped in a local minimum of the cost function. Experimental results show that this method can get very close to the global minimum of the cost function with a small number of iterations. Hence, an analog simulation program, such as SPICE, can be used for the evaluation of the cost function at each iteration. I. INTRODUCTION There is an increasing trend towards the integration of analog blocks in ASIC circuits. Despite the great effort that has been made in the development of CAD tools for analog and mixed circuits, the design of the analog part of a chip continues to be a bottleneck [1][2]. Different optimization tec...
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"... Abstract — The electronics industry is increasingly focused on the consumer marketplace, which requires lowcost highvolume products to be developed very rapidly. This, combined with advances in deep submicron technology have resulted in the ability and the need to put entire systems on a single c ..."
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Abstract — The electronics industry is increasingly focused on the consumer marketplace, which requires lowcost highvolume products to be developed very rapidly. This, combined with advances in deep submicron technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixedsignal systemsonchip presents enormous challenges both to the designers of the chips and to the developers of the CAD systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large singlechip mixedsignal systems and how CAD systems are expected to develop to overcome these issues. Index Terms — Design methodology, design automation, mixed analogdigital integrated circuits, hardware design languages, simulation, integrated circuit layout, integrated circuit modeling, and testing. I.