Results 1  10
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14
Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layout Designs
 IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems
, 1995
"... With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. ..."
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Cited by 48 (4 self)
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With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation.
GradientBased Optimization of Custom Circuits Using a StaticTiming Formulation
, 1999
"... This paper describes a method of optimally sizing digital circuits on a statictiming basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradientbased, nonlinear optimization and can accom ..."
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Cited by 26 (4 self)
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This paper describes a method of optimally sizing digital circuits on a statictiming basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradientbased, nonlinear optimization and can accommodate transistorlevel schematics without the need for precharacterization. It employs efficient timedomain simulation and gradient computation for each channelconnected component. A largescale, generalpurpose, nonlinear optimization package is used to solve the tuning problem. A prototype tuner has been developed that accommodates combinational circuits consisting of parameterized library cells. Numerical results are presented.
UncertaintyAware Circuit Optimization
 IN DAC
, 2002
"... Almost by definition, welltuned digital circuits have a large number of equally critical paths, which form a socalled "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies i ..."
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Cited by 19 (1 self)
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Almost by definition, welltuned digital circuits have a large number of equally critical paths, which form a socalled "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, modeltohardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater. Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertaintyaware" mode has been implemented and applied to several highperformance microprocessor macros. Numerical results are included.
Noise Considerations in Circuit Optimization
 In Proc. International Conference on ComputerAided Design
, 1998
"... Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is particularly susceptible to chargesharing and coupling noise. Thus the design and optimization of a circuit should take noise ..."
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Cited by 13 (0 self)
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Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is particularly susceptible to chargesharing and coupling noise. Thus the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semiin nite constraints. In addition, the number of signals to be checked and the number of subintervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper describes a novel method for incorporating noise considerations during automatic circuit optimization. Semiin nite constraints representing noise considerations are rst converted toordinary equality constraints involving time integrals, which are readily computed in the context of circuit optimization based on timedomain simulation. Next, the gradients of these integrals are computed by the adjoint method. By using an augmented Lagrangian optimization merit function, the adjoint method is applied tocompute all the necessary gradients required for optimization in a single adjoint analysis, no matter how many noise measurements are considered and irrespective of the dimensionality of the problem. Numerical results are presented. 1
TwoStep Algorithms for Nonlinear Optimization with Structured Applications
 SIAM Journal on Optimization
, 1999
"... In this paper we propose extensions to trustregion algorithms in which the classical step is augmented with a second step that we insist yields a decrease in the value of the objective function. The classical convergence theory for trustregion algorithms is adapted to this class of twostep alg ..."
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Cited by 10 (6 self)
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In this paper we propose extensions to trustregion algorithms in which the classical step is augmented with a second step that we insist yields a decrease in the value of the objective function. The classical convergence theory for trustregion algorithms is adapted to this class of twostep algorithms. The algorithms can be applied to any problem with variable(s) whose contribution to the objective function is a known functional form. In the nonlinear programming package LANCELOT, they have been applied to update slack variables and variables introduced to solve minimax problems, leading to enhanced optimization eciency. Extensive numerical results are presented to show the eectiveness of these techniques. Keywords. Trust regions, line searches, twostep algorithms, spacer steps, slack variables, LANCELOT, minimax problems, expensive function evaluations, circuit optimization. AMS subject classications. 49M37, 90C06, 90C30 1 Introduction In nonlinear optimization proble...
Optimization of Custom MOS Circuits by Transistor Sizing
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1996
"... Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to r ..."
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Cited by 9 (4 self)
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Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design highperformance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses
Analysis and Optimization of Structured Power/Ground Networks
 IEEE Trans. Computeraided Design
, 2003
"... This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes which are hard to analyze efficiently, and treestru ..."
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Cited by 7 (0 self)
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This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes which are hard to analyze efficiently, and treestructured networks, which provide poor performance. As an example, we consider a P/G network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. A fast and efficient eventdriven P/G network simulator is proposed, which hierarchically simulates the P/G network with an adaptation of PRIMA to handle nonzero initial conditions. An adjoint network that incorporates the variable topology of the original P/G network, as elements switch in and out of the network, is constructed to calculate the transient adjoint sensitivity over multiple intervals. The gradients of the most critical node with respect to each wire width and decap are used by a sensitivitybased heuristic optimizer that minimizes a weighted sum of the wire and the decap area. Experimental results show that this procedure can be used to efficiently optimize large networks. I.
Circuit Optimization via Adjoint Lagrangians
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1997
"... The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable paramete ..."
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Cited by 6 (3 self)
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The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method [2] is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method [1] is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper, we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmentedLagrangianbased optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program. The adjoint
Fast decap allocation algorithm for robust onchip power delivery
 in: Proceedings of International Symposium on Quality Electronic Design (ISQED), 2005
"... Adding onchip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fast decap allocation algorithm, which is able to confine the voltage fluctuations below user specified threshold by adding ..."
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Cited by 4 (2 self)
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Adding onchip decoupling capacitors (decaps) is an effective way to reduce voltage noise in power/ground networks and ensure robust power delivery. In this paper, we present a fast decap allocation algorithm, which is able to confine the voltage fluctuations below user specified threshold by adding decaps in an area efficient way. The new algorithm adopts the recently proposed timedomain adjoint network method for sensitivity calculation. To avoid the time consuming line search at each iteration in conjugate gradient method, we proposed a simple, yet efficient search step computation method to accelerate the optimization process. The experimental results show that the proposed algorithm is at least 10X faster than the fastest conjugate gradient method reported so far with similar optimization results. 1
Onchip decoupling capacitor budgeting by sequence of linear programming
 in IEEE International Conference on Application Specific Integrated Circuits(ASICON
, 2005
"... Excessive power supply noise increases propagation delay of switching gates and reduces noise margin of the circuit. Adding onchip decoupling capacitors (decaps) is an effective way to reduce voltage noise in a onchip power delivery system. In this paper, we propose an efficient and novel algorith ..."
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Cited by 2 (1 self)
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Excessive power supply noise increases propagation delay of switching gates and reduces noise margin of the circuit. Adding onchip decoupling capacitors (decaps) is an effective way to reduce voltage noise in a onchip power delivery system. In this paper, we propose an efficient and novel algorithm to allocate decaps in an area efficient way. The new algorithm applies the sequence of linear programming based approach to searching the minimum decap area to reduce voltage drop below user specified threshold. We show existing sensitivity based decap allocation algorithms tend to over estimate the decap areas due to nonlinear sensitivity dependence on decap values. Experimental results show that the proposed algorithm uses significantly less decap area than the existing conjugate gradient based approach but with similar CPU runtimes. 1