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Optimization of Custom MOS Circuits by Transistor Sizing
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1996
"... Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to r ..."
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Cited by 9 (4 self)
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Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design highperformance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses
Generalized Constraint Generation for Analog Circuit Design
 in Proc. IEEE ICCAD
, 1993
"... A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from highlevel performance specifications by means of sensitivity ..."
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Cited by 8 (5 self)
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A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from highlevel performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graphbased techniques to extract the necessary geometric information. 1 Introduction The design of analog circuits is often a difficult task compared with a digital one of similar complexity because of the higher number of specifications and the importance of second order effects. In addition, the continuously growing complexity of analog integrated circuits has required a better control over the design quality and the redefinition of tasks like module generation and floorplanning. The performances of...
Circuit Optimization via Adjoint Lagrangians
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1997
"... The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable paramete ..."
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Cited by 6 (3 self)
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The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method [2] is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method [1] is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper, we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmentedLagrangianbased optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program. The adjoint
Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times
 In Proc. IEEE Design, Automation, and Test in Europe Conference
, 2007
"... Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/h ..."
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Cited by 4 (1 self)
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Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(τ) =0 derived using statetransition functions, and then solving this equation by NewtonRaphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C 2 MOS latch/register structures, obtaining speedups of 410 × over the current standard of binary search. I.
Generalized constraint generation in the presence of nondeterministic parasitics
 In Proc. IEEE International Conference on Computer Aided Design
, 1996
"... In a constraintdriven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the cons ..."
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Cited by 2 (2 self)
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In a constraintdriven layout synthesis environment, parasitic constraints are generated and implemented in each phase of the design process to meet a given set of performance specifications. The success of the synthesis phase depends in great part on the effectiveness and the generality of the constraint generation process. None of the existing approaches to the constraint generation problem however are suitable for a number of parasitic effects in active and passive devices due to nondeterministic process variations. To address this problem a novel methodology is proposed based on the separation of all variables associated with nondeterministic parasitics, thus allowing the translation of the problem into an equivalent one in which conventional constrained optimization techniques can be used. The requirements of the method are a welldefined set of statistical properties for all parasitics and a reasonable degree of linearity of the performance measures relevant to design. 1
Constraint Transformation for IC Physical Design
 IEEE Transactions on Semiconductor Manufacturing
, 1999
"... In a topdown design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divideandconquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministi ..."
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In a topdown design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divideandconquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrialstrength applications.