: Motivated by emerging battery operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit and technology optimizations. An architectural based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption. 1.0 Introduction With much of research efforts of the past ten years directed toward increasing the speed of digital systems, present-day technologies possess computing capabilities which make possible powerful personal workstations, sophisticated computer graphics, and multi-media capabilities such as real-time speech recognition and...

: Processors used in portable systems must provide highly energy-efficient operation, due to the importance of battery weight and size, without compromising high performance when the user requires it. The user-dependent modes of operation of a processor in portable systems are described and separate metrics for energy efficiency for each of them are found to be required. A variety of well known low-power techniques are re-evaluated against these metrics and in some cases are not found to be appropriate leading to a set of energy-efficient design principles. Also, the importance of idle energy reduction and the joint optimization of hardware and software will be examined for achieving the ultimate in lowenergy, high-performance design. 1. Introduction The recent explosive growth in portable electronics requires energy conscious design, without sacrificing performance. Simply increasing the battery capacity is not sufficient because the battery has become a significant fraction of the t...

Abstract — Recently reported logic style comparisons based on full-adder circuits claimed complementary passtransistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangementsdemonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-bit adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits, if low voltage, low power, and small power-delay products are of concern. Index Terms — Adder circuits, CPL, complementary CMOS, low-voltage low-power logic styles, pass-transistor

Traditionally, VLSI architects and designers have acknowledged the area, performance, and effort tradeoffs between cell-based and full-custom implementations of the same datapath function. However, few attempts have been made to characterize these tradeoffs in the context of contemporary fabrication processes and area place and route tools. More importantly, few attempts have been made to determine how to enable cell-based implementations to approach the density and speed of full-custom designs. This work quantifies the limits of cell-based datapath implementations based on results derived from a detailed analysis of the density and performance tradeoffs in the implementation of two full-custom datapaths, the Integer Register-Read Datapath (IRRDP) and the 64-bit adder/subtracter (ADDSUB), employed in the multi-ALU Processor (MAP) chip. A cell-based implementation of the IRRDP is 1.64x larger than the full-custom original. The critical timing path for the cell-based implementation is 11...

The portable communications industry’s vision of integrating a complete multimedia complex on a single die, coupled with the desktop computing industry’s vision of inte-grating multimedia functionality into general-purpose microprocessors has trans-formed lowering the power dissipation of digital signal processing (DSP) datapath circuits into an increasingly important challenge in current and future fabrication pro-cesses. Fully-static CMOS logic accompanied with supply voltage scaling has enjoyed widespread usage in lowering datapath power dissipation over the last decade. How-ever, fundamental limitations preclude device threshold voltage scaling under the con-stant drain-source field scaling paradigm in future deep-submicron processes, imposing limitations on voltage scaling. This has motivated a strong necessity for exploring new methodologies to lower the power dissipation of next-generation high-speed datapath circuits. This thesis investigates Mixed Swing techniques for reducing the power dissipa-tion of static CMOS datapath operators while retaining their high performance, or

Introduction This chapter describes a methodology for designing digital VLSI neurochips which emphasizes area, power, and performance estimation to facilitate architectural exploration in the early stages of design. It first discusses some key aspects of mapping neural net algorithms onto VLSI architectures. It then introduces a set of circuit level building blocks commonly used in constructing digital nets. It discusses how to estimate chip area, performance, and power consumption in architectures constructed from these blocks, showing how to include technology scaling rules in the estimation process. It concludes with a detailed discussion of a CMOS implementation of a digital Boltzmann machine. 2 Mapping algorithms to architectures An algorithm is a set of tasks to be applied to data in a specified order to transform inputs and internal state to desired outputs. An architecture is a set of resources and interconnections. Mapping algorithms to architectures

Abstract not found

In this paper we present a Low Voltage Differential Current Switch Logic (LVDCSL) gate which is capable of achieving high performance for large fan-in gates. High fan-in is enabled by allowing large stacked NMOS tree heights using a pre-discharged NMOS tree, at the same time the power penalty of an increased number of internal nodes in the gate is mitigated by restricting internal node voltage swings. It is topologically a Cascode Voltage Switch Logic Gate with a cross-coupled inverter based load. However, unlike other DCVS gates with cross-coupled inverters, it is fairly robust and relatively insensitive to load imbalances at the output. The salient features of this low-voltage DCSL family are: high speed for high fan-in large stack height NMOS trees, low power due to restricted internal voltage swings and a latching nature which locks out inputs once outputs are evaluated. While the gate exhibits spikes at its differential outputs (in common with other sense-amp based CVSL logic gate...

Abstract-Motivated by emerging battery-operated applica-tions that demand intensive computation in portable environ-ments, techniques are investigated which reduce power con-sumption in CMOS digital circuits while maintaining coniputational throughput. Techniques for low-power opera-tion are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is pre-sented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This op-timum is achieved by trading increased silicon area for reduced power consumption. I.

Asynchronous design has been considered to avoid problems like high clock frequency generation and distribution, as well as high static power consumption in GaAs digital circuits. This paper discusses the real advantages of implementing such circuits with respect to feasibility, speed performance, power dissipation and ease of design migration from CMOS to GaAs while taking into account several approaches. MESFET differential structures prove the most efficient way to implement such circuits. Comparisons between DPTL, DCVS and DC 2 FL are carried out. Finally, some MESFET C-element (Muller's cell) implementations are also described and evaluated. 1.Introduction Gallium Arsenide (GaAs) has been for a long time presented as the future state-of-the-art IC technology for very high-speed VLSI systems. Appealing well known III-V compound physical properties, such as higher electron mobility, higher intrinsic bulk resistivity, higher radiation hardness and wider operating temperature range...