Results 1 
3 of
3
New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
Abstract

Cited by 34 (1 self)
 Add to MetaCart
(Show Context)
Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.
Gate Sizing for Constrained delay/power/area optimization
 in IEEE Transcation on VLSI Design
, 1997
"... Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to mini ..."
Abstract

Cited by 31 (0 self)
 Add to MetaCart
(Show Context)
Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some userdefined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technologydependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on reallife large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I.
Integrated Resynthesis for Low Power
, 1996
"... Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay constraints. It produces 24 % savings in power.