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New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
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Cited by 34 (1 self)
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Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.
Gate Sizing for Constrained delay/power/area optimization
 in IEEE Transcation on VLSI Design
, 1997
"... Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to mini ..."
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Cited by 31 (0 self)
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Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some userdefined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technologydependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on reallife large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I.
Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint
 Proc. of Int'l Symp. on Low Power Design, Monterey CA
, 1995
"... We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fanout l ..."
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Cited by 21 (0 self)
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We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fanout load should be enlarged to minimize the power consumption of the circuit. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor a ecting the power optimal size. We extend our model to analyze powerdelay characteristic of a CMOS circuit and derive the powerdelay optimal size of a transistor. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. Experimental results (SPICE simulations) are presented to con rm the correctness of our analytical model. 1
Integrated Resynthesis for Low Power
, 1996
"... Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the ..."
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Cited by 4 (0 self)
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Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay constraints. It produces 24 % savings in power.
Algorithms for the Electrical Optimization of Digital MOS Circuits
"... This work addresses the problem of automating the electrical optimization of digital MOS circuits. Improvements to a circuit's speed, area, and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or cloc ..."
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This work addresses the problem of automating the electrical optimization of digital MOS circuits. Improvements to a circuit's speed, area, and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area or power. These algorithms have been incorporated iL:o a prototype electrical optimization tool, EO, that assists the designer in the performance tuning of MOS VLSI circuits. The designer provides the circuit Ia you t and the requirements on its speed, power consumption, and area. EO identifies the slowest paths through the circuit and computes the optimal transistor sizes to achieve the performance objectives. This frees the designer to deal more directly with the speed, poRer, and area characteristics of the circuit rather than the details of its implementation. Due to the fast inieractive response of the tool, the designer can experiment with a large number of different transistor sizing options to determine the best balance of delay vs. area, delay vs. power, and power vs. area. The transistor sizing algorithms compute optimal points so that the designer is guaranteed of making the most efficient possible tradeoffs of scarce resources. When compared to manual designs, the circuits produced by EO are typically faster or have substantially lower power consumption and area. I.