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An Efficient Method for LargeScale Gate Sizing
 IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications
"... Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by ..."
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Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by using standard interiorpoint methods for small and mediumsize problems with up to several thousand gates. In this paper, we describe a new method for solving this problem that handles far larger circuits, up to a million gates, and is far faster. Numerical experiments show that our method can compute an adequately accurate solution within around 200 iterations; each iteration, in turn, consists of a few passes over the circuit. In particular, the complexity of our method, with a fixed number of iterations, is linear in the number of gates. A simple implementation of our algorithm can size a 10 000 gate circuit in 25 s, a 100 000 gate circuit in 4 min, and a million gate circuit in 40 min, approximately. For the million gate circuit, the associated GP has three million variables and more than six million monomial terms in its constraints; as far as we know, these are the largest GPs ever solved. Index Terms—Gate sizing, geometric programming (GP), largescale optimization. I.
Abstract Optimal Bus Sizing in Migration of Processor Design
"... The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor ..."
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Cited by 5 (4 self)
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The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimallytuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sumofdelays problem. An iterative algorithm to find the optimallytuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed. 1
Timing optimization of interconnect by simultaneous netordering, wire sizing and spacing
 Proc. ISCAS'06
, 2006
"... Abstract – This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are optimally shared for circuit timing optimization. Using an Elmore delay model including cross capacitances for a ..."
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Cited by 3 (3 self)
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Abstract – This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are optimally shared for circuit timing optimization. Using an Elmore delay model including cross capacitances for a bundle of wires, we show that an optimal wire ordering is uniquely determined, such that best timing can be obtained by proper allocation of wire widths and interwire spaces. The optimal order, called BMI (Balanced Monotonic Interleaved) depends only on the size of drivers for a wide range of cases. Heuristics are presented for simultaneous ordering, sizing and spacing of wires. Examples for 90nanometer technology are analyzed and discussed.
Fast interconnect synthesis with layer assignment,” ISPD
, 2008
"... As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as b ..."
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Cited by 3 (2 self)
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As technology scaling advances beyond 65 nanometer node, more devices can fit onto a chip, which implies continued growth of design size. The increased wire delay dominance due to finer wire widths makes design closure an increasingly challenging problem. Interconnect synthesis techniques, such as buffer insertion/sizing and wire sizing, have proven to be the critical part of a successful timing closure optimization tool. Layer assignment, which was traditionally treated as same as wire sizing, is more effective and friendly in the design flow than wire sizing in the advanced technologies. Techniques for simultaneous layer assignment and buffer insertion with resource control are increasingly important for the quality of results of interconnect synthesis. This paper outlines the importance of layer assignment over wire sizing, and presents efficient techniques to perform concurrent buffer insertion and layer assignment to fix the electrical and timing problems, while maintaining speed and efficient use of resources.
Optimal resizing of bus wires in layout migration
 Proc. ICECS 2004
, 2004
"... Abstract – The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of processing technology, because wire resistance and cross capacitances become more important with scaling. In this paper, timing optimization of signal busses is perfor ..."
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Cited by 2 (0 self)
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Abstract – The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of processing technology, because wire resistance and cross capacitances become more important with scaling. In this paper, timing optimization of signal busses is performed by resizing and spacing individual bus wires, while the total area of the whole bus structure is regarded as a fixed constraint. Properties of optimal bus layouts are proven, and an iterative algorithm to find the optimal wire widths and spaces is presented. Examples of solutions are shown. Guidelines for design are derived from these results. I.
THE RETIMING AND ROUTING OF VLSI CIRCUITS
, 1998
"... In this thesis, we explore three problems arising during the logic synthesis and physical design stages of VLSI circuit design. We rst present a new formulation for the retiming of singlephase clocked circuits containing latches. Then, we discuss crosstalk optimization in channelbased routings, a ..."
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In this thesis, we explore three problems arising during the logic synthesis and physical design stages of VLSI circuit design. We rst present a new formulation for the retiming of singlephase clocked circuits containing latches. Then, we discuss crosstalk optimization in channelbased routings, and nally present a new performancedriven algorithm for the layer assignment of critical global nets. Although singlephase clocked circuits containing latches are in widespread use, there is no existing practical formulation for such circuits that allows retimingbased optimizations. We present anovel, ILPbased formulation for the retiming of such circuits. This formulation can be used to optimize any linearizable objective function. As examples, we discuss the optimization of the clock period and the area of such circuits. Our experiments demonstrate that our approach ise cient and generates ILPs that are easy to solve. We address the increased importance of crosstalk avoidance in deep sub
On Optimal Ordering of Signals in Parallel Wire Bundles
"... Abstract — Optimal ordering and sizing of wires in a constrainedwidth interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average de ..."
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Cited by 1 (1 self)
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Abstract — Optimal ordering and sizing of wires in a constrainedwidth interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the MCF ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet nearoptimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65 nanometer process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10 % in wire delay, translated to about 5 % improvement in the clock cycle of a highperformance microprocessor implemented in that technology. Index Terms — routing, wire ordering, wire spacing C I.
A Performancedriven Layer Assignment Algorithm for Multiple Interconnect Trees
, 1998
"... With the advent of DSM technologies, interconnect delays increasingly overshadow the transistor delays. Furthermore, since the electrical characteristics of di erentlayers in multilayer routing technologies vary widely, the assignment of the interconnect tree edges to speci c routing layers has a la ..."
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With the advent of DSM technologies, interconnect delays increasingly overshadow the transistor delays. Furthermore, since the electrical characteristics of di erentlayers in multilayer routing technologies vary widely, the assignment of the interconnect tree edges to speci c routing layers has a large impact on the interconnect delays. Traditionally, critical global interconnect trees were routed greedily, one at a time. This caused the \good " layers to be used up largely for the rst few trees, yielding poor routings for the remaining trees. Multiple passes with di erent tree orderings were usually used to remedy the situation, although with limited success. We propose the use of dynamically adjusted area quotas to prevent the rst few trees from monopolizing the \good" layers. Our approach is independent of the routing model or the router employed, and reduces the maximum tree delays by around 15 % as compared to traditional algorithms. 1
Wire Sizing with Scattering Effect for Nanoscale Interconnection
"... Abstract—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physicsbased models, whil ..."
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Abstract—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay significantly. Existing works on scattering effect are mostly performed using very complicated physicsbased models, while the scattering impact on nanoscale VLSI interconnect and optimization have not been studied. In this paper, we first present a simple, closedform scattering effect resistivity model based on extensive empirical studies on measurement data. Then we apply the proposed scattering model to revisit several classic wire sizing/shaping problems. Our experimental results show that if the scattering effect is ignored or characterized inaccurately beyond 65nm, the resulting interconnect optimization might be way off from the real optimal solution, e.g., up to 70 % underestimation of the delay, or 20x oversizing. We also obtain the new closedform wiresizing functions with consideration of scattering effects. A I
BoundedSkew Clock and Steiner Routing Under Elmore Delay
, 1995
"... : We study the minimumcost boundedskew routing tree problem under the Elmore delay model. We present two approaches to construct boundedskew routing trees: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to the boundariesof merging regions, an ..."
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: We study the minimumcost boundedskew routing tree problem under the Elmore delay model. We present two approaches to construct boundedskew routing trees: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to the boundariesof merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and dynamic programming to consider merging points that are interior to, rather than on the boundary of, the merging regions. Our new algorithms allow accurate control of Elmore delay skew, and show the utility of merging points inside merging regions. 1 Introduction Control of signal delay is important in layout synthesis of high performance systems. Recent works on clock routing have accomplished exact zero skew under the Elmore delay model [17, 5, 11], and given new singlelayer (planar) constructions [18, 15, 16]. A detailed review of clock tree and Steiner routing algorithms is given in [14]. ...