One of the fundamental challenges for modern highperformance network interfaces is the processing capabilities required to process packets at high speeds. Simply transmitting or receiving data at gigabit speeds fully utilizes the CPU on a standard workstation. Any processing that must be done to the data, whether at the application layer or the network layer, decreases the achievable throughput. This paper presents an architecture for offloading a significant portion of the network processing from the host CPU onto the network interface. A prototype, called the GRIP (Gigabit Rate IPSec) card, has been constructed based on an FPGA coupled with a commodity Gigabit Ethernet MAC. Experimental results based on the prototype are presented and analyzed. In addition, a second generation design is presented in the context of lessons learned from the prototype. 1.

The performance requirements of applications have continuously superseded the computing power of architecture platforms. Increasingly larger number of transistors available on a chip have resulted in complex architectures and integration of various architecture components on the chip. But, the incremental performance gains obtained are lower as the complexity and the integration increase. Reconfigurable architectures can adapt the behavior of the hardware resources to a specific computation that needs to be performed. Computing using reconfigurable architectures provides an alternate paradigm to utilize the available logic resources on the chip. For several classes of applications, reconfigurable computing promises several orders of magnitude speed-up compared to conventional architectures. This article provides a brief insight into the architectures, models and algorithms which facilitate reconfigurable computing. 1 Introduction Microprocessors are at the heart of most curr...

Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently selected Advanced Encryption Standard (AES) is slowly replacing older ciphers as the building block of choice for secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a single-core AES FPGA implementation. This work provides a more thorough description of the defining AES hardware characteristics than is currently available in the research literature, along with implementation results that are pareto optimal in terms of throughput, latency, and area efficiency. 1

Reconfigurable computing is a new paradigm based on dynamically adapting the hardware to reconfigure the computation and communication structures on the chip. Re-configurable circuits and systems have evolved fromapplication specific accelerators to a general purpose computing paradigm. Various reconfigurable devices have been de-veloped by researchers and the industry. These devices promise a high degree of flexi-bility and superior performance. But, the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. This thesis addresses the fundamental challenges in achieving high performance us-ing reconfigurable architectures. The diverse range of issues in mapping applications onto reconfigurable architectures are identified. A formal framework for mapping ap-plication tasks onto reconfigurable architectures is proposed in this thesis. The pro-posed framework includes a parameterized system level model, algorithmic mapping techniques and system level interpretive simulation environment. A parameterized model of hybrid reconfigurable architectures, Hybrid System Ar-chitecture Model (HySAM), is developed to facilitate application mapping. Hybrid re-configurable architectures include traditional processing units and memory on the same die as reconfigurable logic. The parameterized abstract model, HySAM, is general enough to capture a wide range of configurable systems. Loop statements in traditional pro-grams consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This thesis develops a for-mal methodology for mapping loops onto reconfigurable architectures. The abstract model is used to define and solve the problem of mapping loop statements onto reconfig-urable architectures. The complexity of the problems and our proposed solutions is also addressed. Performance improvements are achieved on various architectures using our algorithmic techniques for mapping. In addition, existing design and simulation tools do not include the reconfiguration aspect in their methodology. A simulation methodology for reconfigurable architectures is proposed and validated by implementing a proof of concept tool. The Dynamically Reconfigurable systems Interpretive simulation and Vi-sualization Environment (DRIVE) facilitates high level performance evaluation frame-work for design space exploration.

With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. What Beowulf clusters lack in technology, they more than make up for with their significant cost advantage over traditional supercomputers. This paper presents the cost implications of an architectural extension that adds reconfigurable computing to the network interface of Beowulf clusters. A quantitative idea of cost-effectiveness is formulated to evaluate computing technologies. Here, cost-effectiveness is considered in the context of two applications: the 2D Fast Fourier Transform (2D-FFT) and integer sorting.

Despite a decade of research into their use for computing applications, FPGA-based custom computing machines are still only used to accelerate a limited range of applications. Recognizing that recent advances in network technology provide an opportunity for a more general-purpose application of custom computing machines, we develop the idea of an intelligent network adapter for cluster-based parallel computing, calling the resulting architecture an Adaptable Computing Cluster. Results presented suggest that placing the FPGAs in the data path to the network dramatically improves the performance and scalability of target applications. This is especially noteworthy because the target applications have historically not performed well on either technology. This paper discusses how FPGAs can be used to provide network functionality while increasing compute power. The focus is on a specific application, the 2D Fast Fourier Transform, with additional insights into the implications for parallel computing on a cluster.

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The new-found ubiquity of embedded processors in consumer and industrial applications brings with it an intensified focus on security, as a strong level of trust in the system software is crucial to their widespread deployment. The growing area of software protection attempts to address the key steps used by hackers in attacking a software system. In this paper, we introduce a unique approach to embedded software protection that utilizes a hardware/software codesign methodology. Results demonstrate that this framework can be the successful basis for the development of embedded applications that meet a wide range of security and performance requirements.

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