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35
Efficient DDDbased Symbolic Analysis of Large Linear Analog Circuits
, 2001
"... A new technique for generating approximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term generation algorithm is given and its performan ..."
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A new technique for generating approximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term generation algorithm is given and its performance is compared to a matroidbased algorithm. Experimental results indicate that our approach is the fastest reported algorithm so far for this application.
MIDAS  a functional simulator for mixed digital and analog sampled data systems
, 1995
"... Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering  Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated ci ..."
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Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering  Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).
A flexible topology selection program as part of an analog synthesis system
 In European Design and Test Conference (ED&TC
, 1995
"... The task of a topology selector within an analog synthesis system is to find the best available analog circuit topology out of a library for a given set of input specifications. The proposed selection method consists of a combination of two approaches: procedural filtering and rulebased filtering. ..."
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The task of a topology selector within an analog synthesis system is to find the best available analog circuit topology out of a library for a given set of input specifications. The proposed selection method consists of a combination of two approaches: procedural filtering and rulebased filtering. The procedural filtering consists of two consecutive phases based on boundary checking and interval analysis. Such a combination of different sorts of filtering is a new technique that allows an optimal tradeoff between selection accuracy and required selection time. The tool that implements the method is technology independent and fully open towards newly added design knowledge. 1
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics
 In Proceedings Design Automation and Test in Europe Conference
, 2002
"... This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a templatebased fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the genera ..."
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This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a templatebased fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the generated expressions enables the use of efficient geometric programming techniques when using these expressions for circuit sizing and optimization. Attention is paid to estimating the relative `goodnessoffit' of the generated expressions. Experimental results illustrate the capabilities of the approach.
Templatefree symbolic performance modeling of analog circuits via canonicalform functions and genetic programming
 IEEE Trans. on CAD
, 2009
"... Abstract—This paper presents CAFFEINE, a method to automatically generate compact, interpretable symbolic performance models of analog circuits with no prior specification of an equation template. CAFFEINE uses SPICE simulation data, to model arbitrary nonlinear circuits and circuit characteristics ..."
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Abstract—This paper presents CAFFEINE, a method to automatically generate compact, interpretable symbolic performance models of analog circuits with no prior specification of an equation template. CAFFEINE uses SPICE simulation data, to model arbitrary nonlinear circuits and circuit characteristics. CAFFEINE expressions are canonical form functions: productofsum layers alternating with sumofproduct layers, as defined by a grammar. Multiobjective genetic programming trades off error with model complexity. On test problems, CAFFEINE models demonstrate lower prediction error than posynomials, splines, neural networks, kriging, and support vector machines. This paper also demonstrates techniques to scale CAFFEINE to larger problems.
Circuit complexity reduction for symbolic analysis of analog integrated circuits
 in Proc. DAC
, 1999
"... This paper presents a method to reduce the complexity of a linear or linearized (smallsignal) analog circuit. The reduction technique, based on qualityerror ranking, can be used as a standard reduction engine that ensures the validity of the resulting network model in a specific (set of) design po ..."
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This paper presents a method to reduce the complexity of a linear or linearized (smallsignal) analog circuit. The reduction technique, based on qualityerror ranking, can be used as a standard reduction engine that ensures the validity of the resulting network model in a specific (set of) design point(s) within a given frequency range and a given magnitude and phase error. It can also be used as an analysis engine to extract symbolic expressions for poles and zeroes. The reduction technique is driven by analysis of the signal flow graph associated with the network model. Experimental results show the effectiveness of the approach. 1
Hierarchical Symbolic Analysis of Analog Circuits Using TwoPort Networks
"... Abstract: This paper presents a method towards hierarchical symbolic analysis of linear analog circuits using twoport networks. The important difference to the ordinary flat symbolic analysis is, that we treat the transistor pairs as blocks and then derive the transfer function with network analyzer ..."
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Abstract: This paper presents a method towards hierarchical symbolic analysis of linear analog circuits using twoport networks. The important difference to the ordinary flat symbolic analysis is, that we treat the transistor pairs as blocks and then derive the transfer function with network analyzer without to setup and solve a complicated DAE system for a whole analog circuit. The hierarchical idea can be even used to large circuits in divide and conquer manner. Experimental results obtained with some applications of this method are presented. Key–Words: Symbolic analysis, Twoport network 1
Hierarchical Characterization of Analog Integrated CMOS Circuits
 Proc Design Automation and Test in Europe
, 1998
"... This paper presents a new method for hierarchical characterization of analog integrated circuits. For each circuit class, a fundamental set of performances is defined and extracted topologyindependently. A circuit being characterized is decomposed in general subcircuits. Sizing rules of these topol ..."
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This paper presents a new method for hierarchical characterization of analog integrated circuits. For each circuit class, a fundamental set of performances is defined and extracted topologyindependently. A circuit being characterized is decomposed in general subcircuits. Sizing rules of these topologyindependent subcircuits are included into the characterization by functional constraints. In this way, bad circuit sizing is detected and located. 1.
(SEMI)SYMBOLIC MODELING OF LARGE LINEAR SYSTEMS: PENDING ISSUES
"... The paper deals with some open problems from the area of symbolic and semisymbolic modeling of linear systems, focusing on combining the symbolic, semisymbolic and numeric computation. ..."
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Cited by 3 (2 self)
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The paper deals with some open problems from the area of symbolic and semisymbolic modeling of linear systems, focusing on combining the symbolic, semisymbolic and numeric computation.
Symbolic Analysis of Linear Circuits with Modern Active Elements
"... Abstract: The paper deals with the symbolic analysis of linear circuits with modern active elements using the SNAP program. The simulator can perform both classical and approximate analyses. All device models are stored in a text library, which can be easily extended. Device parameters can be defin ..."
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Abstract: The paper deals with the symbolic analysis of linear circuits with modern active elements using the SNAP program. The simulator can perform both classical and approximate analyses. All device models are stored in a text library, which can be easily extended. Device parameters can be defined as simple symbols or as formulae in the netlist. This allows the simulation of electronic circuits both with basic elements and with complex behavioral models.