We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal trade-o s among competing performance measures such aspower, open-loop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal trade-o curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a

Abstract—This paper presents a novel procedure for predicting integrated circuit parametric performance and yield when provided with sample transistor test results and a circuit schematic. Two enhancements to the existing Monte Carlo simulation procedures are described: 1) a multivariate nested model is used to reproduce random process-induced device variations, rather than the multivariate multinormal model typically used, and 2) the stochastic Monte Carlo method for mapping process variability into a performance distribution is replaced with a deterministic mapping technique. The use of multivariate nested distributions allows estimation not only of correlation between various model parameters, but also allows each of those variations to be apportioned among the various stages of the process (i.e., wafer to wafer, lot to lot, etc.). This allows matched devices to be more accurately simulated, without having to develop customized models for each configuration of matching, and provides focus for process improvement efforts into those areas with the maximum potential reward. The use of deterministic mapping provides simulation results which are repeatable and do not rely on chance to insure that the process parameter space has been evenly explored. A software package which implements the entire procedure has been written in C++. Index Terms—Monte Carlo simulation, multivariate statistics, parametric yield.

A new technique for generating approximate symbolic expressions for network functions in linear(ized) analog circuits is presented. It is based on the compact determinant decision diagram (DDD) representation of the circuit. An implementation of a term generation algorithm is given and its performance is compared to a matroidbased algorithm. Experimental results indicate that our approach is the fastest reported algorithm so far for this application.

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extracted from the sized component netlist produced by the synthesis tool, in terms of characteristic behavior of the components and various voltage and current laws. For the synthesized implementation to be correct, it must imply a formal model extracted from a user given behavior specification. Circuit implementation and expected behavior are both modeled in the PVS higher-order logic proof checker as linear functions and the PVS decision procedures are used to prove the implication. 1 Introduction The challenges in formally verifying an analog design are some what different from those in verifying digital designs. Analog components exhibit continuous time behavior often represented as an...

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both obtained with this method, insight into the nonlinear operation of analog integrated circuits can be gained. For accurate distortion computations, the accuracy of the transistor models is critical. A MOS transistor model is discussed that allows us to explain the measured fourth-order nonlinear behavior of a 1-GHz CMOS upconverter. Further, the method is illustrated with several examples, including the analysis of an operational amplifier up to its gain-bandwidth product. This example has also been verified experimentally. Index Terms---Analog integrated circuits, harmonic distortion, nonlinear ...

This paper introduces an automated circuit design system for the evolution and subsequent invention of CMOS amplifiers. The proposed system relies on a mix of genetic programming and a new topologyindependent design optimisation method referred to as current-flow analysis. Genetic programming evolves new circuit topologies from the collection of primitive devices and basic building blocks. Current-flow analysis screens and corrects circuits using topology-independent design rules. Experimental results show a promising improvement on the design of operational amplifiers that making the automated analogue design environment using genetic programming a lot more practical. I.

In recent years, the technique of simpl$cation during gen-eration has turned out to be very promising for the eficient computation of approximate symbolic network functions for large transistor circuits. In this paper it is shown how sym-bolic network functions can be simpl$ed during their genera-tion with any well-known symbolic network analysis method. The underlying algorithm for the different techniques is al-ways a matroid intersection algorithm. It is shown that the most eflcient technique is the two-graph method. An imple-mentation of the simpltjication during generation technique with the two-graph method illustrates its benefits for the sym-bolic analysis of large analog circuits. 1

This paper presents a novel method to automatically generate symbolic expressions for both linear and nonlinear circuit characteristics using a template-based fitting of numerical, simulated data. The aim of the method is to generate convex, interpretable expressions. The posynomiality of the generated expressions enables the use of efficient geometric programming techniques when using these expressions for circuit sizing and optimization. Attention is paid to estimating the relative `goodness-of-fit' of the generated expressions. Experimental results illustrate the capabilities of the approach.

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state-of-the-art in this field is also studied, pointing out directions for future research. 1. INTRODUCTION Circuit analysis is a basic milestone for efficient design of integrated circuits. Ever since powerful computers have been available, designers have developed programs to analyze circuits automatically. Today, all electrical engineering professionals and students use electrical simulators (such as HSPICE or ELDO). However, electrical simulators do not cover all the analysis tasks required for integrated circuit design. Essentially, they only serve to verify the performance of previously sized circuits. Among other things, designers must be able to predict the behavior of unsized circuits by tracing relationships among performance figures and design parameters. These relationships may be in the form of transfer functions, poles and ...