In this paper we present a model for diagnosis of errors in Sequential Multi-Valued Logic Networks (SMVLN). The method allows not only to detect errors in an implementation, but also identifies the fault location. In contrast to many previously presented approaches this model does not consider a specific implementation. Instead the model assumes tests based on the transition behavior of the corresponding MVL Finite State Machine (FSM) on the functional level. We present a method for constructing a minimal cost test based on AND/OR graphs using tests with MV outcomes. The model enables encoding over twovalued circuits as well as consideration of SMVLNs. The new approach provides efficient solution even for large MVL FSMs with up to 50000 states. Experimental results for randomly generated FSMs are given that demonstrate the efficiency of our approach. 1 Introduction Several circuit design methods for Multi-Valued Logic (MVL) have been proposed in the past few years [3, 6]. These new ...