With Q’s in the tens to hundreds of thousands, micromachined vibrating resonators are proposed as integratedcircuit-compatible tanks for use in the low phase-noise oscillators and highly selective filters of communications subsystems. To date, LF oscillators have been fully integrated using merged CMOS/microstructure technologies, and bandpass filters consisting of spring-coupled micromechanical resonators have been demonstrated in a frequency range from HF to VHF. In particular, two-resonator micromechanical bandpass filters have been demonstrated with frequencies up to 35 MHz, percent bandwidths on the order of 0.2%, and insertion losses less than 2 dB. Higher order three-resonator filters with frequencies near 455 kHz have also been achieved, with equally impressive insertion losses for 0.09 % bandwidths, and with more than 64 dB of passband rejection. Additionally, free-free-beam single-pole resonators have recently been realized with frequencies up to 92 MHz and ’s around 8000. Evidence suggests that the ultimate frequency range of this high- tank technology depends upon material limitations, as well as design constraints, in particular, to the degree of electromechanical coupling achievable in microscale resonators.

Abstract—A modification of stacked spiral inductors increases the self-resonance frequency by 100 % with no additional processing steps, yielding values of 5 to 266 nH and self-resonance frequencies of 11.2 to 0.5 GHz. Closed-form expressions predicting the self-resonance frequency with less than 5 % error have also been developed. Stacked transformers are also introduced that achieve voltage gains of 1.8 to 3 at multigigahertz frequencies. The structures have been fabricated in standard digital CMOS technologies with four and five metal layers. Index Terms—Inductors, oscillators, quality factor, RF circuits, self-resonance frequency, stacked spirals, transformers, tuned amplifiers.

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Abstract—In this paper, a closed-form integral representation for the eddy-current losses over a conductive substrate is presented. The results are applicable to monolithic inductors and transformers, especially when such structures are realized over an epitaxial CMOS substrate. The technique is verified against measured results from 100 MHz to 14 GHz for spiral inductors. Index Terms—CMOS substrate losses, eddy currents, monolithic inductors, monolithic transformers, spiral inductors, spiral transformers. I.

Abstract—This paper presents a physically based compact model for estimating high-frequency performance of spiral inductors. The model accurately accounts for skin and proximity effects in the metal conductors as well as eddy current losses in the substrate. The model shows excellent agreement with measured data mostly within 10 % across a variety of inductor geometries and substrate dopings up to 20 GHz. A web-based spiral inductor synthesis and analysis tool COILS, which makes use of the compact models, is presented. An optimization algorithm using binary searches speeds up the synthesis of inductor designs. Index Terms—Eddy current, ground shield, inductor, patterned ground shield, proximity effect, Q-factor, radio-frequency (RF) integrated circuit, skin effect, spiral inductor. I.

This report contains a review of CMOS process technology in terms of radio-frequency (RF) performance around and beyond 1GHz. First, the use of integrated technology for wireless communications is justified and state-of-the-art commercial chipsets are presented. After CMOS is presented as a potential RF candidate, the major elements of the technology are evaluated in an RF context and current performance is listed. Elements include substrate, transistors, interconnects, passive devices, packaging technology, and design tools. Also the on-going process innovations are reviewed, and their impact on RF measures is discussed. T HE last few years, the wireless services industry has grown tremendously [70]. Due to the acceptance of the Internet, higher efficiency/mobility needs, and the massive advertisement performed by eager service provides, the requirements for more sophisticated wireless services are ever increasing [11, 40]. To get everyone connected "anywhere and anytime" is ...

The expansion of the market for portable wireless communication devices has given a tremendous push to the development of a new generation of low-power radio frequency integrated circuit (RFIC) products. In this fast-growing environment where time-to-market constraints force tight schedules, having a good design methodology, innovative computer-aided design (CAD) tools, and a well-integrated design system are key factors to success. In this paper, we describe a design system developed to provide the designer with everything necessary to accurately predict the behavior of RFIC devices, including layout and package parasitic effects. We show how important a well-defined and integrated system is to manufacturing a design that meets specifications at the minimum cost, in the minimum time. A close link between schematic, models, and layout is of paramount importance to ensure the accuracy needed for low-power RF design. We give an overview of the advanced methods and tools currently available for simulation and noise analysis of RF devices. Finally, we show a design example that obtained first-silicon success. Keywords—Design automation, design methodology, design system, device modeling, layout design, layout parasitics, low power, power amplifier, RF integrated circuit design, RF integrated circuit simulation, substrate coupling, substrate noise. I.

Software radio architecture can support multiple standards by performing analog-to-digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP Σ∆) ADC based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining iii the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe

Abstract — A reconfigurable, differentially driven symmetric inductor is presented. This inductor is used in a differential LC-VCO, which is implemented in a 0.35 µm SiGe-BiCMOS-process. The output frequency of the LC-VCO covers twice the frequencies of the DECTand the ISM-band (3.76 GHz... 3.86 GHz respectively 4.8 GHz... 4.967 GHz). The maximum simulated Qfactor of the inductor at differential excitation is about 10 at 3.86 GHz for the low frequency range and about 5.8 at 4.967 GHz for the high frequency range. The simulated phase noise of the differential VCO is −137 dBc/Hz at 6.4 MHz offset for the low frequency band and −119 dBc/Hz at 2.5 MHz offset for the high frequency band. For both frequency ranges the VCO consumes a supply current of 3.3 mA at a 3.3 V power supply voltage.