We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology. Global Design of Analog Cells using Statistical Optimization Techniques 3 Global Desig...

DSYN generates optimized Digital/Analog Converter (DAC) layouts given a set of specifications including performance constraints, a description of the implementation technology, and a set of design parameters. The generation process consists of a synthesis step followed by a layout step. During synthesis a new constrained optimization method is coupled with combination of circuit simulation and DAC design equations. The layout step uses stretching and tiling operations on a set of primitive cells. Prototypes have been demonstrated for an 8-bit, 100-MS/s specification, driving a 37.5-ohm video load, and a static 10-bit specification, driving a 4mA full-scale output current. Both designs use a 5-V supply in a 1.2 m CMOS process. 1 Biographies Robert R. Neff (member) was with the University of California, Berkeley, CA. He is now with Hewlett Packard Company, Palo Alto, CA 94304. Paul R. Gray (fellow) and Alberto Sangiovanni-Vincentelli (fellow) are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 . Coorespondence should be directed to: Dr. Robert Neff Hewlett Packard Company 3500 Deer Creek Road, MS 26U-4 Palo Alto, CA 94304-0867 Phone: (415)857-6220 Fax: (415)857-3637 E-mail: neff@hpl.hp.com 1. This research was supported by the Semiconductor Research Corporation under grant 94-DC-324. 2 I.

In this paper a new topology optimization feature of a module generator environment [5-6] will be presented. The optimization is performed by removing redundant elements of objects already placed and by assessing different layout topologies of a module. This drastically reduces the length of the generator source code, because different topologies need no separate source code, but result automatically.

The electronics industry is increasingly focused on the consumer marketplace, which requires low-cost high-volume products to be developed very rapidly. This, combined with advances in deep sub-micron technology have resulted in the ability and the need to put entire systems on a single chip. As more of the system is included on a single chip, it is increasingly likely that the chip will contain both analog and digital sections. Developing these mixed-signal systems-on-chip presents enormous challenges both to the designers of the chips and to the developers of the CAD systems that are used during the design process. This paper presents many of the issues that act to complicate the development of large single-chip mixed-signal systems and how CAD systems are expected to develop to overcome these issues.

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Abstract—This paper presents an optimized methodology to folded cascode operational transconductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. Using 0.35µm CMOS process, the designed folded cascode OTA achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz in strong inversion mode. In moderate inversion mode, it has a 92dB DC gain and provides a gain bandwidth product of around 69MHz. The OTA circuit has a DC gain of 75.5dB and unity-gain frequency limited to 19.14MHZ in weak inversion region. Keywords—CMOS IC design, Folded Cascode OTA, gm/ID methodology, optimization. I.

In this paper, the design strategy for a circuit synthesis program is described. Unlike other synthesis programs, the program searches in an extremely large set of possible circuits (over 1,000,000 possible circuit configurations), and is not restricted to one device technology. It uses

In this paper a new topology optimization feature of a module generator environment [5-6] will be presented. The optimization is performed by removing redundant elements of objects already placed and by assessing different layout topologies of a module. This drastically reduces the length of the generator source code, because different topologies need no separate source code, but result automatically. 1