We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal trade-o s among competing performance measures such aspower, open-loop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal trade-o curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach. Keywords--- Layout, Analog Design, Constraint-Driven Layout. I. Introduction The layout of analog circuits is intrinsically more difficult than the d...

A CAD tool for analog circuit synthesis is presented. This tool, called FASY, uses fuzzy–logic based reasoning to select one topology among a fixed set of alternatives. For the selected topology, a two–phase optimizer sizes all elements to satisfy the performance constrains minimizing a cost function. In FASY, the decision rules used in the topology selection process are introduced by an expert designer or automatically generated by means of a learning process that uses the optimizer mentioned above. The capability of learning topology selection rules by experience, is unique in FASY. Practical examples demonstrate the tool ability of this tool to learn topology selection rules and to synthesize analog cells with different circuit topologies. 1 1

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural layout approach is shown to be best suited for this kind of methodologies. Once captured, the procedural description can be used several times to calculate both rapidly and accurately all parasitics that appear during physical realizations without layout generation. Efficient algorithms are developed to take into account analog layout constraints such as matching, parasitic control, shape and reliability considerations. This allows to account for these effects early in the design which guarantees the fulfillment of the required performance specifications, permits to optimize various design aspects in the presence of parasitics and shortens the overall design time by avoiding laborious sizing-layout iterations. An example of a high performance OTA is presented at the end to illustrate the effectiveness of the approach.

This paper introduces an automated circuit design system for the evolution and subsequent invention of CMOS amplifiers. The proposed system relies on a mix of genetic programming and a new topologyindependent design optimisation method referred to as current-flow analysis. Genetic programming evolves new circuit topologies from the collection of primitive devices and basic building blocks. Current-flow analysis screens and corrects circuits using topology-independent design rules. Experimental results show a promising improvement on the design of operational amplifiers that making the automated analogue design environment using genetic programming a lot more practical. I.

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...

We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a geometric program, a special type of convex optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected.

In order to reach the Shannon limit, researchers have found more e#cient error control coding schemes. However, the computational complexity of such error control coding schemes is a barrier to implementing them. Recently, researchers have found that bioinspired analog network decoding is a good approach with better combined power/speed performance than its digital counterparts. However, the lack of CAD (computer aided design) tools makes the analog implementation quite time consuming and error prone. Meanwhile, the performance loss due to the nonidealities of the analog circuits has not been systematically analyzed. Also, how to organize analog circuits so that the nonideal e#ects are minimized has not been discussed.

Given a combinatorial optimization problem specified by a finite set of configurations or states S and by a cost function C defined on all the states j in S, the SA algorithm is characterized by a rule to generate randomly a new configuration with a certain probability, and by a random acceptance rule according to which the new configuration is accepted or rejected. A parameter T controls the acceptance rule. The generic structure of the algorithm is presented in Fig.1. Theoretical investigations of the SA optimization technique have been reported in some literatures [8].