Abstract not found

In this paper we present a repeater block planning algorithm forinterconnect-centric floorplanning. We introduce the concept of

In this paper, we develop a multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation. Fast global routing is achieved using a fast two-bend routing and incremental A-tree algorithm. The routing congestion is modeled by the wire usage estimated by the fast global router. A hierarchical area density control is developed for placing objects with significant size variations. Experimental results show that, compared to GORDIAN-L, the wire length-driven MGP is 4--6.7 times faster and generates slightly better wire length for test circuits larger than 100 000 cells. Moreover, the congestion-driven MGP improves wiring overflow by 45%--74% with 5% larger bounding box wire length but 3%--7% shorter routing wire length measured by a graph-based A-tree global router.

This paper presents an interconnect-driven floorplanning (IDFP) flow and algorithm integrated with multi-layer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer insertion, wire sizing and spacing. It also includes fast routability estimation and performance-driven routing for congestion control. Our experiments on the SUN picoJava-II TM core test circuit show that over 74% delay reduction can be achieved using our interconnect-driven floorplanner, compared to a conventional floorplanner without consideration of interconnect performance optimization/planning. We expect that IDFP with GWP will play a central role in designing interconnect-limiting, high-performance integrated circuits. 1 Introduction Global interconnect is commonly recognized as a key factor for designing high-performance integrated circuits, as VLSI process technology migrates into...

traditionalfl oorplanners, area minimization is an important issue. However, due to the recent advances in VLSI technology, the number of transistors in a design are increasing rapidly and so are their switching speeds. This has increased the importance of interconnect delay and routability in the overall performance of a circuit. We should consider interconnect planning, bu#er planning and routability as early as possible. In this paper, we study and implement a routability-drivenfl oorplanner with congestion estimation and bu#er planning. Our method is based on a simulated annealing approach that is divided into two phases: the area optimization phase and the congestion optimization phase. In the area optimization phase, modules are roughly placed according to the total area and wirelength. In the congestion optimization phase, afl oorplan will be evaluated by its area, wirelength, congestion and routability. We assume that every bu#er should be inserted at afl exible interval from each other for long enough wires and probabilistic analysis is performed to compute the congestion information taken into accounts the constraints in bu#er locations. Our approach is able to reduce the average number of wires at the congested areas and allow more feasible insertions of bu#ers to satisfy the delay constraints without having much penalty in increasing the area of the fl orplan.

Abstract — As technology advances and the number of interconnections among modules rapidly increases, timing closure and design convergence are the most important concerns. Hence, it is desirable to consider interconnect optimization as early as possible. In this paper, we first address simultaneous floorplanning and buffer block planning (i.e., integrating buffer block planning into floorplanning) for interconnect optimization. Experimental results show that our method can significantly improve the interconnect delay and reduce the number of buffers needed. I.

Abstract — Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing congestion. Using a probabilistic technique instead of a global router has the advantage of speed and easy updating. Previously proposed probabilistic models [1] [2] do not account for wiring that may already be fixed in the design, e.g., due to macro blocks or power rails. These “partial wiring blockages ” certainly influence the global router, so they should also influence a probabilistic routing prediction algorithm. This work proposes a probabilistic congestion prediction metric that extends the work of [2] to model partial wiring blockages. We also show a new fast algorithm to efficiently generate the congestion map and demonstrate the effectiveness of our methods on real routing problems. I.

In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that a net will pass through each particular location of a floorplan taken into account buffer locations and routing blockages. Experimental results show that our congestion model can optimize congestion and delay (by successful buffer insertions) of a circuits better with only a slight penalty in area.

Memory accesses represent a major bottleneck in embedded systems power and performance. Traditionally, designers tried to alleviate this problem by relying on a simple cache hierarchy, or a limited use of special purpose memory modules such as stream buffers. Although real-life applications contain a large number of memory references to a diverse set of data structures, a significant percentage of all memory accesses in the application are generated from a few memory instructions that exhibit predictable, well-known access patterns; this creates an opportunity for memory customization, targeting the needs of these access patterns. We present APEX, an approach that extracts, analyzes and clusters the most active access patterns in the application, and aggressively customizes the memory architecture to match the needs of the application. Moreover, though the memory modules are important, the rate at which the memory system can produce the data for the CPU is significantly impacted by the connectivity architecture between the memory subsystem and the CPU. Thus, it is critical to consider the connectivity architecture early in the design flow, in conjunction with the memory architecture. We couple the exploration of memory modules together with their connectivity, to evaluate a wide range of cost, performance, and energy connectivity architectures. We use a heuristic to prune the design space, guiding the exploration towards the most promising designs. We present experiments on a set of large real-life benchmarks, showing significant performance improvements for varied cost and power characteristics, allowing the designer to evaluate customized memory and connectivity configurations for embedded systems.

In traditional floorplanners, area minimization is an important issue. However, due to the recent advances in VLSI technology, the number of transistors in a design are increasing rapidly and so are their switching speeds. This has increased the importance of interconnect delays and routability in the overall performance of the circuit. We should consider interconnect planning, buffer planning and routability as early as possible. In this paper, we study and implement a routability-driven floorplanner with congestion estimation and buffer planning. Our method is based on a simulated annealing approach that is divided into two phases: the area optimization phase and the congestion optimization phase. In the area optimization phase, modules are roughly placed according to the total area and wirelength. In the congestion optimization phase, a floorplan will be evaluated by its area, wirelength, congestion and routability. We assume that buffers should be inserted at a flexible interval from each other for long enough wires and probabilistic analysis is performed to calculate the congestion information taken into accounts the constraints in buffer locations. Our approach is able to reduce the average number of wires at the congested areas and allow more feasible insertions of buffers to satisfy the delay constraints without having much penalty in increasing the area of the floorplan.