Results 1  10
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25
PerformanceDriven Interconnect Design Based on Distributed RC Delay Model
 in Proc. Design Automation Conf
, 1993
"... In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimizat ..."
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Cited by 69 (21 self)
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In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or nearoptimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for highperformance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, ...
Optimal Wiresizing Under the Distributed Elmore Delay Model
 in Proc. Int. Conf. on Computer Aided Design
, 1993
"... In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we deve ..."
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Cited by 56 (26 self)
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In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we develop a polynomialtime optimal wiresizing algorithm for arbitrary interconnect structures under the distributed Elmore delay model. Extensive experimental results show that our wiresizing solution reduces interconnection delay by up to 51% when compared to the uniformwidth solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model in [7], our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnection delays to the timingcritical sinks by up to 12%. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, interconnection delay has...
A Unicastbased Approach for Streaming Multicast
, 2001
"... Network layer multicast is know as the most efficient way to support multicast sessions. However, for security, QoS and other considerations, most of the realtime application protocols can be better served by upper layer (transport or application) multicast. In this paper we propose a scheme called ..."
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Cited by 29 (0 self)
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Network layer multicast is know as the most efficient way to support multicast sessions. However, for security, QoS and other considerations, most of the realtime application protocols can be better served by upper layer (transport or application) multicast. In this paper we propose a scheme called MRTP for multicast RTP sessions. The idea behind this scheme is to set up the multicast RTP session over a set of unicast RTP sessions, established between the various participants (source and destinations) of the multicast session. We then address the issue of finding a set of paths with maximum bottleneck for an MRTP session. We show that this problem is NPComplete, and propose several heuristics to solve it.
A Survey on MultiNet Global Routing for Integrated Circuits
 Integration, the VLSI Journal
, 2001
"... This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential ..."
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Cited by 28 (4 self)
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This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential routing and ripupandreroute, and then discusses multicommodity flow based methods, which have attracted a good deal of attention recently. The family of hierarchical routing techniques and several of its variants are then overviewed, in addition to other techniques such as movebased heuristics and iterative deletion. While many traditional techniques focus on the conventional objective of managing congestion, newer objectives have come into play with the advances in VLSI technology. Specifically, the focus of global routing has shifted so that it is important to augment the congestion objective with metrics for timing and crosstalk. In the later part of this paper, we summarize the recent progress in these directions. Finally, the survey concludes with a summary of
On Crossing Minimization Problem
, 1998
"... In this paper we consider a problem related to global routing postoptimization: the crossing minimization problem (CMP). Given a global routing representation, the CMP is to minimize redundant crossings between every pair of nets. In particular, there are two kinds of CMP: constrained CMP (CCMP) an ..."
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Cited by 19 (4 self)
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In this paper we consider a problem related to global routing postoptimization: the crossing minimization problem (CMP). Given a global routing representation, the CMP is to minimize redundant crossings between every pair of nets. In particular, there are two kinds of CMP: constrained CMP (CCMP) and unconstrained CMP (UCMP). These problems have been studied previously in [Groe89], where an O(m 2 n) algorithm was proposed for CCMP, and in [MS95], where an (mn 2 +¸ 2 ) algorithm was proposed for UCMP, where m is the total number of modules, n is the number of nets, and ¸ is the number of crossings defined by an initial global routing topology. We present a simpler and faster O(mn) algorithm for CCMP and an O(n(m + ¸)) time algorithm for UCMP. Both algorithms improve over the time bounds of the previously proposed algorithms. The novel part of our algorithm is that it uses the plane embedding information of globally routed nets in the routing area to construct a graphbased framewo...
A Timingconstrained Simultaneous Global Routing Algorithm
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2002
"... In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any singlenet routing algorithm and any delay model in global routing. It is bas ..."
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Cited by 15 (6 self)
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In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any singlenet routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities that can be exploited for congestion reduction under timing constraints. These flexibilities are expressed through the concepts of a soft edge and a slideable Steiner node. Starting with an initial solution where timing driven routing is performed on each net without regard to congestion constraints, this algorithm hierarchically bisects a routing region and assigns soft edges to the cell boundaries along the bisector line. The assignment is
On HighSpeed VLSI Interconnects: Analysis and Design
 Proc. AsiaPacific Conf. on Circuits and Systems
, 1992
"... We survey our recent work in the analysis and design of interconnect topologies for highspeed VLSI. Results include: a new, fast distributed RLC analysis method based on a twopole approximation; an Atree formulation for performancedriven interconnect; an optimal wiresizing algorithm; and new cri ..."
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Cited by 12 (8 self)
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We survey our recent work in the analysis and design of interconnect topologies for highspeed VLSI. Results include: a new, fast distributed RLC analysis method based on a twopole approximation; an Atree formulation for performancedriven interconnect; an optimal wiresizing algorithm; and new criticalpath dependent routing tree algorithms. 1 Introduction Interconnection design is becoming a major concern in the design of highspeed systems, where stateoftheart integrated circuits use submicron technology and operate at multigiga hertz clock rates. In this range, optimization based on the traditional layout design objective, i.e. minimization of chip area, no longer suffices since the emphasis on system performance requires different consideration. For instance, the minimum Steiner tree has traditionally been the preferred interconnect topology because: (1) it uses the minimum wiring area and (2) minimum wiring area results in minimum wire capacitance, which is the dominant fac...
A Catalog of Hanan Grid Problems
 Networks
, 2000
"... We present a general rectilinear Steiner tree problem in the plane and prove that it is solvable on the Hanan grid of the input points. This result is then used to show that several variants of the ordinary rectilinear Steiner tree problem are solvable on the Hanan grid, including  but not li ..."
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Cited by 11 (2 self)
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We present a general rectilinear Steiner tree problem in the plane and prove that it is solvable on the Hanan grid of the input points. This result is then used to show that several variants of the ordinary rectilinear Steiner tree problem are solvable on the Hanan grid, including  but not limited to  Steiner trees for rectilinear (or isothetic) polygons, obstacleavoiding Steiner trees, group Steiner trees and prizecollecting Steiner trees. Also, the weighted region Steiner tree problem is shown to be solvable on the Hanan grid; this problem has natural applications in VLSI design routing. Finally, we give similar results for other rectilinear problems. 1 Introduction Assume we are given a finite set of points S in the plane. The Hanan grid H(S) of S is obtained by constructing vertical and horizontal lines through each point in S. The main motivation for studying the Hanan grid stems from the fact that it is known to contain a rectilinear Steiner minimum tree (RSMT)...
Geometric Interconnection and Placement Algorithms
, 1995
"... This dissertation examines a number of geometric interconnection, partitioning, and placement problems arising in the field of VLSI physical design automation. In particular, many of the results concern the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength ..."
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Cited by 10 (3 self)
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This dissertation examines a number of geometric interconnection, partitioning, and placement problems arising in the field of VLSI physical design automation. In particular, many of the results concern the geometric Steiner tree problem: given a set of terminals in the plane, find a minimumlength interconnection of those terminals according to some geometric distance metric. Two new algorithms are introduced that compute optimal rectilinear Steiner trees. Both are provably faster than any previous algorithm for instances small enough to solve in practice, and both are also fast in practice. The first algorithm is a dynamic programming algorithm based on decomposing a rectilinear Steiner tree into full trees. A full tree is a Steiner tree in which every terminal is a leaf. Its time complexity is O(n3^n), where n is the number of terminals. The second algorithm modifies the first by the use of fullset screening, which is a process by which some candidate full trees are eliminated f...
An ILP based hierarchical global routing approach for VLSI ASIC design
, 2007
"... The use of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and intercon ..."
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Cited by 8 (2 self)
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The use of integrated circuits in highperformance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today’s chip designs. Global routing is one of the key subproblems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66 % on average for edge capacity model (ECM).