Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space [30]. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tri-state on-chip buses with level or transition signalin...

In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually re-quires a specific test bench or creation of quite complex stimuli. This problem can be avoided with a VHDL model of the bus. In this paper, the bus model concept is discussed. The concept can be applied to serial and parallel, single and multiple master bus modeling on various hierarchical levels. The model includes timing and signaling analysis, master, slave and arbitration modules. ISA (PC/AT) bus is used as an example case of the modeling. 1.