Recent dramatic improvements in integrated circuit fabrication technology have led to Field-Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these large systems often contain memory. Architectural support for the efficient implementation of memory in next-generation FPGAs is therefore crucial. This dissertation examines the architecture of FPGAs with memory,aswell as algorithms that map circuits into these devices. Three aspects are considered: the analysis of circuits that contain memory as well as the automated random generation of such circuits, the architecture and algorithms for stand-alone con#gurable memory devices, and architect...

. In this paper, we review parallel metaheuristics for approximating the global optimal solution of combinatorial optimization problems. Recent developments on parallel implementation of genetic algorithms, simulated annealing, tabu search, variable neighborhood search, and greedy randomized adaptive search procedures (GRASP) are discussed. 1. Introduction Search techniques are fundamental problem-solving methods in computer science and operations research. Search algorithms have been used to solve many classes of problems, including path-finding problems, two-player games, and constraint satisfaction problems. Classical examples of path-finding problems include many combinatorial optimization problems (e.g. integer programming) and puzzles (e.g. Rubic's cube, Eight Puzzle). Chess, backgammon, and Othello belong to the class of two player games, while a classic example of a constraint satisfaction problem is the eight-queens problem. In this paper, we focus on NP-hard combinator...

Abstract-One way to alleviate the heavy computation required by simulated annealing placement algorithms is to replace a significant fraction of the higher or middle temperatures with a faster heuristic, and then follow it with simulated annealing. A crucial issue in this ap-proach is the determination of the starting temperature for the simu-lated annealing phase-a temperature should be chosen that causes an appropriate amount of optimization to he done, but makes good use of the structure provided by the heuristic. This paper presents a method for measuring the temperature of an existing placement. The approach is based on the measurement of the probability distribution of the change in cost function, P(AC), and makes the assumption that the placement is in simulated annealing equilibrium at some temperature. The temperature of placements produced both by a simulated anneal-ing and a min-cut placement algorithm are measured, and good agree-ment with known temperatures is obtained. The P ( A C) distribution

Abstract. In this paper, we review parallel search techniques for approximating the global optimal solution of combinatorial optimization problems. Recent developments on parallel implementation of genetic algorithms, simulated annealing, tabu search, and greedy randomized adaptive search procedures (GRASP) are discussed.

I hereby declare that I am the sole author of this thesis. I authorize the University of Guelph to lend this thesis to other institutions or individuals for the purpose of scholarly research. I further authorize the University of Guelph to reproduce this thesis by photo-copying or by other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. ii The University of Guelph requires the signatures of all persons using or photo-copying this thesis. Please sign below, and give address and date. iii iv A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity

Metaheuristic parallel search methods -- tabu search, simulated annealing and genetic algorithms, essentially -- are reviewed, classified and examined not according to particular methodological characteristics, but following the unifying approach of the level of parallelization. It is hoped that by examining the commonalities among parallel implementations across the field of metaheuristics, insights may be gained, trends may be discovered, and research challenges may be identified. Particular attention is paid to applications of parallel metaheuristics to transportation problems.

A new row-based parallel algorithm for standard-cell placement targeted for execution on a hypercube multiprocessor is presented. Key features of this implementation include a dynamic simulated-annealing schedule, row-partitioning of the VLSI chip image, and two novel approaches to control error in parallel cellplacement algorithms: (1) Heuristic Cell-Coloring; (2) Adaptive Sequence Length Control. 1. INTRODUCTION Simulated annealing is a general-purpose optimization method that has been successfully applied to solve a large variety of combinatorial optimization problems including many in VLSI design. Annealing is computationally very expensive, hence efforts to improve execution time has proceeded along two fronts: (1) accelerating the annealing schedule, and (2) parallelizing the annealing algorithm for execution on multiprocessors. Parallel implementations of annealing as applied to the cell placement application either attempt multiple cell moves in parallel [1-7], or distribute ...

. Simulated annealing is an algorithm which generates near-optimal outcomes to combinatorial optimization problems. It is commonly thought to be slow. Cost-function approximation and parallel processing increase simulated annealing speed, but they can cause inaccuracies that degrade the outcome. Prior theoretical work has not adequately related cost-function inaccuracy to the run-time or quality of the outcome. We prove these results about annealing with inaccurate cost-functions: 1) Expected cost at equilibrium is exponentially affected by fl=T , where fl limits cost-function rangeerrors and T gives the temperature. 2) Expected cost at equilibrium is exponentially affected by (oe 2 \Gamma oe 2 )=2T 2 , when the errors have a Gaussian distribution. 3) Constraining fl to a constant factor of T guarantees convergence under a 1= log t temperature schedule. 4) A similar constraint guarantees convergence for a fractal space with a geometric temperature schedule. 5) Inaccuracies worse...

A common approach to parallelizing simulated annealing to generate several perturbations to the currentsolutionsimultaneously, requiring synchronization to guarantee correct evaluation of the cost function. The cost of this synchronization may be reduced by allowing inaccuracies in the cost calculations. We provide a framework for understanding the theoretical implications of this approach based on a model of processor interaction under reduced synchronization that demonstrates how errors in cost calculations occur and how to estimate them. We showhow bounds on error in the cost calculations in asimulated annealing algorithm can be translated into worst-case bounds on perturbations in the parameters which describe the behavior of the algorithm.

A ncw row-bas & panllcl algorithm for standard-ccll placement targeted for execution on a hypercube multiprocessor is prescntcd. Key fcatures of this implementation include a dynamic simulated-annealing schcdule, row-partitioning of the VLSI chip image, and two novel new approaches to controlling error in parallel ccll-placemcnt algorithms: Heuristic Cell-Coloring and Adaptive (Parallel Move) Sequence Control. Heuris-tic Cell-Coloring idcntifics scts of noninteracting cells that can be moved repeatedly. and in parallel, with no buildup of error in the placement cost. Adaptive Scquencc Control allows multiple parallel cell moves to. take place between global cell-position "updates. " This fecdback mechanism is based on an error bound we derive analytically from thc traditional annealing move-acccpmce profile. We present placement rcsults for rcai industry circuits and summarize the performance of an implementa-tion on the Intcl iPSC/2 Hypercubc. The runtime of his algorithm is 5 to 16 times faster than a previous pro-gram developed for the Hypcrcubc. while producing equivalent quality placement. An integrated place and route program for thc Intcl iPSC/2 Hypercube is currently being developed around this kernel algorithm. =CEDING PAGE BLANK NOT iii