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27
A Solution Methodology for Exact Design Space Exploration in a ThreeDimensional Design Space
 IEEE Trans. on VLSI Systems
, 1997
"... This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing ..."
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Cited by 20 (2 self)
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This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a 3dimensional (3D) design space: the usual 2D design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to a 3D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through: (1) a careful selection of candidate clock lengths, and (2) tight bounds on the number of functional units or on the schedule length. Both chaining and multicycle operations are supported. I. Introduction Highlevel synthesis is the design task of converting a behavioral description of a digital system into a registertransfer level design that implements that behavior. One of the cen...
A Fast Approach to Computing Exact Solutions to the ResourceConstrained Scheduling Problem
 ACM TRANS. DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1997
"... This paper presents an algorithm that substantially reduces the computational effort required to obtain the exact solution to the Resource Constrained Scheduling (RCS) problem. The reduction is obtained by (a) using a branchandbound search technique, which computes both upper and lower bounds, and ..."
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Cited by 17 (3 self)
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This paper presents an algorithm that substantially reduces the computational effort required to obtain the exact solution to the Resource Constrained Scheduling (RCS) problem. The reduction is obtained by (a) using a branchandbound search technique, which computes both upper and lower bounds, and (b) using ecient techniques to accurately estimate the possible timesteps at which each operation can be scheduled and using this to prune the search space. Results on several benchmarks with varying resource constraints indicate the clear superiority of the algorithm presented here over traditional approaches using integer linear programming, with speedups of several orders of magnitude.
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
 In 9th International Symposium on System Synthesis
, 1996
"... One of the most compelling reasons for developing highlevel synthesis systems has been the desire to quickly explore the design space. Since this problem is very difficult to solve optimally, most systems compute either lower bounds or estimates on the optimal tradeoff curve. The methodology describ ..."
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Cited by 10 (3 self)
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One of the most compelling reasons for developing highlevel synthesis systems has been the desire to quickly explore the design space. Since this problem is very difficult to solve optimally, most systems compute either lower bounds or estimates on the optimal tradeoff curve. The methodology described here goes beyond most previous work in several ways: (1) it computes all optimal tradeoff points so as to completely characterize the design space, (2) it solves not only the scheduling problem, but the clock determination and module selection problems as well, and (3) it carefully prunes the search space at each level of the design cycle. 1 Introduction For many years, one of the most compelling reasons for developing highlevel synthesis systems [1, 2] has been the desire to quickly explore a wide range of designs for the same behavioral description. Given a set of designs, two metrics are commonly used to evaluate their quality: area (ideally total area, but often only functional uni...
Approximative Representation of boolean Functions by size controllable ROBDD's
, 1997
"... ROBDD's([2]) are a very popular datastructure for the representation and manipulation of boolean functions. They have tractable sizes for many boolean functions and come up with efficient algorithms for boolean operations. In the worst case however, size and time complexity grows exponentially when ..."
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Cited by 9 (0 self)
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ROBDD's([2]) are a very popular datastructure for the representation and manipulation of boolean functions. They have tractable sizes for many boolean functions and come up with efficient algorithms for boolean operations. In the worst case however, size and time complexity grows exponentially when performing a polynomial number of operations. However, there are applications where an approximate knowledge about a boolean function like a lower or upper bound may be sufficient. In this paper we present a datastructure based on ROBDD's, that allows to trade space and time efficiency for precision. The basic extension is provided by the computation of least upper resp. greatest lower bounds of a boolean function under a size constraint for its ROBDD. As a first practical application we conclude some experimental results for the computation of local don't cares in combinational circuits.
Efficient Optimal Design Space Characterization Methodologies
, 2000
"... This paper presents several methodologies for design space exploration that compute all optimal tradeoff points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes advantage of both the structure within the design space itse ..."
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Cited by 9 (0 self)
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This paper presents several methodologies for design space exploration that compute all optimal tradeoff points for the combined problem of scheduling, clock length determination, and module selection. We discuss how each methodology takes advantage of both the structure within the design space itself as well as the structure of, and interaction between, each of the three subproblems
TEMPLATE: A generic TEchnology Mapping PLATform
 IN PREPARATION, PREPRINTREIHE, INSTITUT F"UR INFORMATIK, UNIVERSIT"AT W"URZBURG
, 1997
"... Technology mapping problems arize in logic synthesis systems, when the gap between a synthesized boolean network and the implementation of that network within a given target technology has to be bridged. This paper presents a modular, versatile technology mapping system that supports many differ ..."
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Cited by 8 (2 self)
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Technology mapping problems arize in logic synthesis systems, when the gap between a synthesized boolean network and the implementation of that network within a given target technology has to be bridged. This paper presents a modular, versatile technology mapping system that supports many different target technologies. Guided by a complexity analysis of the problem, we develop a variety of efficient, exact or heuristic methods for technology driven network clustering. Depending on the target technology and optimization methods and goals, different subnetworks must be provided as candidates for clustering. Methods to achieve this are also included. We conclude with experimental results we obtained with several configurations of the system for different target technologies.
An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments
"... Abstract. With the increasing availability of experimental data on genegene and proteinprotein interactions, modeling of gene regulatory networkshasgainedaspecialattentionlately.Tohaveabetterunderstanding of these networks it is necessary to capture their dynamical properties, by computing its ste ..."
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Cited by 7 (1 self)
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Abstract. With the increasing availability of experimental data on genegene and proteinprotein interactions, modeling of gene regulatory networkshasgainedaspecialattentionlately.Tohaveabetterunderstanding of these networks it is necessary to capture their dynamical properties, by computing its steady states. Various methods have been proposed to compute steady states but almost all of them suffer from the state space explosion problem with the increasing size of the networks. Hence it becomes difficult to model even moderate sized networks using these techniques. In this paper, we present a new representation of gene regulatory networks, which facilitates the steady state computation of networks as large as 1200 nodes and 5000 edges. We benchmarked and validated our algorithm on the T helper model from [8] and performed in silico knock out experiments: showing both a reduction in computation time and correct steady state identification. 1
Node mergers in the presence of don't cares
 Proc. ASPDAC’07
"... Abstract — SAT sweeping is the activity of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent the entire equivalence class. This provides significant advantages in synthesis because it can reduce circuit size and provides additionaly flexibility in t ..."
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Cited by 6 (3 self)
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Abstract — SAT sweeping is the activity of merging two or more functionally equivalent nodes in a circuit by selecting one of them to represent the entire equivalence class. This provides significant advantages in synthesis because it can reduce circuit size and provides additionaly flexibility in technology mapping which could be crucial in postsynthesis optimizations. In addition, it is also critical in verification because it can reduce the complexity of the netlist to be analyzed in equivalence checking. Most algorithms available to this end do not exploit observability don’t cares (ODCs) since they do not lend themselves to symmetric transformations. Although a few recent approaches have proposed solutions that can exploit ODCs by overcoming this limitation, they limit their analysis to just a few levels of surrounding logic due to the elevated computational complexity. We develop an ODCbased node merging algorithm that performs efficient global ODC analysis (considering the entire netlist) through simulation and SAT. Our contributions which enable global ODCbased optimizations are: (1) a fast ODCaware simulator and (2) an incremental verification strategy that limits computational complexity. In addition, our techniques operate on arbitrarily mapped netlists, allowing for powerful postsynthesis optimizations. We show that global ODC analysis discovers up to 60 % more (and 25 % on average) nodemerging opportunities than current stateoftheart solutions based on local ODC analysis. I.
NearOptimal Instruction Selection on DAGs
, 2008
"... Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and ea ..."
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Cited by 5 (2 self)
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Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and easily solved problem, instruction selection on directed acyclic graphs is NPcomplete. In this paper we present NOLTIS, a nearoptimal, linear time instruction selection algorithm for DAG expressions. NOLTIS is easy to implement, fast, and effective with a demonstrated average code size improvement of 5.1 % compared to the traditional tree decomposition and tiling approach.
Cluster assignment for highperformance embedded vliw processors
 ACM Trans. Des. Autom. Electron. Syst
, 2002
"... Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with a large number of register file ports. Efficient utilization of a clustered datapath requires careful binding/assignment of operations to clusters. The article ..."
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Cited by 4 (0 self)
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Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with a large number of register file ports. Efficient utilization of a clustered datapath requires careful binding/assignment of operations to clusters. The article proposes a binding algorithm that effectively explores tradeoffs between incluster operation serialization and delays associated with data transfers between clusters. Extensive experimental evidence is provided showing that the algorithm generates high quality solutions for representative kernels, with up to 33 % improvement over a stateoftheart binding algorithm. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors—Code generation;