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A Flexible LDPC/Turbo Decoder Architecture
- Springer Journal of Signal Processing Systems
, 2011
"... All in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately. ..."
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All in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.
Multi-Layer Parallel Decoding Algorithm and VLSI
- Architecture for Quasi-Cyclic LDPC Codes,” 2010, submitted to IEEE International Symposium on Circuits and Systems
"... Abstract—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The ..."
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Abstract—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a synthesis area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations. I.
VLSI Architecture for Layered Decoding of QC-LDPC codes . . .
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
, 2012
"... In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyc ..."
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In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K ≥ 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z × Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm2, the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations.
Scalable and low power LDPC decoder design using high level algorithmic synthesis
- in Proc. IEEE SoC Conf
, 2009
"... Abstract — This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential untimed ..."
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Abstract — This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential untimed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable parallelism, and (2) multi-layer pipelined decoding architecture to achieve higher throughput. Based on the PICO technology, we have implemented a two-layer pipelined decoder on a TSMC 65nm 0.9V 8-metal layer CMOS technology with a core area of 1.2 mm 2. The maximum achievable throughput is 415 Mbps when operating at 400 MHz clock frequency and the estimated peak power consumption is 180 mW. I.
FPGA Prototyping of A High Data Rate LTE Uplink Baseband Receiver
"... Long Term Evolution (LTE) standard is becoming the appropriate choice to pave the way for the next generation wireless and cellular standards. While the popular OFDM technique has been adopted and implemented in previous standards and also in the LTE downlink, it suffers from high peak-to-averagepow ..."
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Long Term Evolution (LTE) standard is becoming the appropriate choice to pave the way for the next generation wireless and cellular standards. While the popular OFDM technique has been adopted and implemented in previous standards and also in the LTE downlink, it suffers from high peak-to-averagepower ratio (PAPR). High PAPR requires more sophisticated power amplifiers (PAs) in the handsets and would result in lower efficiency PAs. In order to combat such effects, the LTE uplink choice of transmission is the novel Single Carrier Frequency Division Multiple Access (SC-FDMA) scheme which has lower PAPR due to its inherent signal structure. While reducing the PAPR, the SC-FDMA requires a more complicated detector structure in the base station for multi-antenna and multi-user scenarios. Since the multi-antenna and multi-user scenarios are critical parts of the LTE standard to deliver high performance and data rate, it is important to design novel architectures to ensure high reliability and data rate in the receiver. In this paper, we propose a flexible architecture of a high data rate LTE uplink receiver with multiple receive antennas and implemented a single FPGA prototype of this architecture. The architecture is verified on the WARPLab (a software defined radio platform based on Rice Wireless Open-access Research Platform) and tested in the real over-the-air indoor channel. I.
Architecture and VLSI Realization of a High-Speed Programmable Decoder for LDPC Convolutional Codes
, 2008
"... In this paper, we present a novel high-speed dual-core programmable decoder architecture for LDPC convolutional codes and their tail-biting versions. This architecture uses a modified Min-Sum algorithm and enables the decoding of a multitude of codes with different node degree distributions, rates a ..."
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In this paper, we present a novel high-speed dual-core programmable decoder architecture for LDPC convolutional codes and their tail-biting versions. This architecture uses a modified Min-Sum algorithm and enables the decoding of a multitude of codes with different node degree distributions, rates and block lengths. We show how the parallelization concepts are derived using the properties of the bipartite graphs underlying the codes. Moreover, the hardware elements composing the architecture will be presented and analyzed in detail. The programmability of the decoder is also considered. Finally, we present the synthesis results for a prototype ASIC which is capable of achieving high decoding throughput still with very high flexibility, relatively low power consumption and small area.
A New MIMO Detector Architecture Based on a Forward-Backward Trellis Algorithm
- IEEE Asilomar Conference on Signals, Systems and Computers
, 2008
"... Abstract — In this paper, a recursive Forward-Backward (F-B) trellis algorithm is proposed for soft-output MIMO detection. Instead of using the traditional tree topology, we represent the search space of the MIMO signals with a fully connected trellis and a Forward-Backward recursion is applied to c ..."
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Abstract — In this paper, a recursive Forward-Backward (F-B) trellis algorithm is proposed for soft-output MIMO detection. Instead of using the traditional tree topology, we represent the search space of the MIMO signals with a fully connected trellis and a Forward-Backward recursion is applied to compute the a posteriori probability (APP) for each coded data bit. The proposed detector has the following advantages: a) it keeps a fixed throughput and has a regular datapath structure which makes it amenable to VLSI implementation, and b) it attempts to maximize the a posteriori probability by tracing both forward and backward on the trellis and it always ensures that at least one candidate exists for every possible transmitted bit xk ∈ {−1, +1}. Compared with the soft K-best detector, the proposed detector significantly reduces the complexity because sorting is not required, while still maintaining good performance. A maximum throughput of 533Mbps is achievable at a cost of 576K gates for 4 × 4 16-QAM system. I.
DOI 10.1007/s11265-010-0477-6 A Flexible LDPC/Turbo Decoder Architecture
"... Abstract Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most power-ful error correcting codes that are widely used in mod-ern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be re-quired. However, the different decoding a ..."
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Abstract Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most power-ful error correcting codes that are widely used in mod-ern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be re-quired. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a uni-fied message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15 % area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on
software radio
"... Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for ..."
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Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for
