This paper presents algorithms and experimental results for model-checking continuous -time Markov chains (CTMCs) based on a structured analysis approach. In this approach, a CTMC is represented as a term in Kronecker algebra that reects the component structure of the system model. Such representations can be obtained in a natural way from various high-level speci cation formalisms, such as stochastic extensions of Petri nets, process algebras or activity networks. Properties are expressed in Continuous Stochastic Logic (CSL) which includes means to express transient, steady-state and path performance measures. This paper describes novel model-checking algorithms for CSL that fully exploit the compositional description of the CTMC. This yields an eective way to combat the state-space explosion problem and enables the model-checking of fairly large Markov chains. Furthermore, we show how state-space aggregation (modulo bisimulation) and the elimination of vanishing states can be done in a component-wise manner. To demonstrate the applicability of the approach, and to assess the eciency of our algorithms, we analyze a stochastic Petri net-model of a workstation cluster system and a simple queueing network.

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Abstract. We present algorithms for parallel probabilistic model checking on general purpose graphic processing units (GPGPUs). For this purpose we exploit the fact that some of the basic algorithms for probabilistic model checking rely on matrix vector multiplication. Since this kind of linear algebraic operations are implemented very efficiently on GPGPUs, the new parallel algorithms can achieve considerable runtime improvements compared to their counterparts on standard architectures. We implemented our parallel algorithms on top of the probabilistic model checker PRISM. The prototype implementation was evaluated on several case studies in which we observed significant speedup over the standard CPU implementation of the tool. 1

This paper presents a method of modeling on-chip communication behavior of a system as a set of communicating processes to find an optimal bus width and interface buffer size for the communication bus. An assumption for the modeling is that the system has already been partitioned and mapped onto the appropriate components of a SoC. We parameterize the communication behavior of a mixed Hw/Sw system considering the amount of data to be transferred, on-chip bus width, computation time of synthesized hardwares, bus topology and bus protocol. With these parameters we estimate the transition probabilities between the communicating processes and model the overall communication behavior of a system by Markov chain. This model is used to estimate the round trip communication delay and buffer size in the bus-interfaces for different bus widths. From the estimated figures we select the optimal values for those parameters that satisfy given design constraints. The results of applying this approach to an Ogg Vorbis decoder clearly demonstrate the utility of our techniques for modeling communication behavior in order to estimate the bus width and buffer requirements of a complex system.