Results 1 
6 of
6
Maze Routing with Buffer Insertion and Wiresizing
 DAC 2000
, 2000
"... We propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing problem as a graphtheoretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamicprogramming basedtechniques. Routing constraints such as w ..."
Abstract

Cited by 15 (0 self)
 Add to MetaCart
We propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing problem as a graphtheoretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamicprogramming basedtechniques. Routing constraints such as wiring obstacles and restrictions on buffer locations and types are easily incorporated in the formulation. Furthermore, efficient software routines solving shortest path problems in existing graph applic ation libraries can be applied. We construct a BPGraph such that the length of every path in this graph is e qual to the Elmore delay. Therefore, finding the minimum Elmore delay path becomes a finite shortest path problem. The buffer choices and insertion locations are represente d as the vertices in the BPGraph. The interconnect wir es are sized by constructing a lookup table for buffertobuffer wire sizing solutions. We also provide a technique that is able to tremendously improve the runtime. Experiments show improvements over previously proposed methods.
An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs
 in Proc. Int. Symp. on Physical Design
, 1997
"... In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the loc ..."
Abstract

Cited by 7 (2 self)
 Add to MetaCart
In this paper, we formulated a new class of optimization problem, named the general CHposynomial program, which is more general than the simple and boundedvariation CHposynomial programs in [1]. We revealed the general dominance property so that an efficient and unified algorithm based on the local refinement (LR) operation can be used to optimize the simple, boundedvariation and general CHposynomial programs. We applied the LRbased optimization algorithm to solve the device sizing problem using accurate tablebased model, and the wire sizing and spacing problem with consideration of coupling between multiple nets. Both problems are solved in the context of simultaneous device and wire sizing optimization for deep submicron designs. Experiments show that our LRbased optimization algorithm is very effective and extremely efficient. Up to 16.5% delay reduction is observed when compared with previous work based on the simple device model [1], and up to 31% delay reduction and 100x speedup is observed when compared the global interconnect sizing and spacing work [2]. We believe that our general CHposynomial formulation and LRbased algorithm can also be applied to other optimization problems in the CAD field.
Theory and Algorithm of LocalRefinement Based Optimization with Application to Device and Interconnect Sizing
, 1999
"... In this paper we formulate three classes of optimization problems: the simple, monotonicallyconstrained, and bounded CHprograms. We reveal the dominance property under the local refinement (LR) operation for the simple CHprogram, as well as the general dominance property under the pseudoLR opera ..."
Abstract

Cited by 7 (7 self)
 Add to MetaCart
In this paper we formulate three classes of optimization problems: the simple, monotonicallyconstrained, and bounded CHprograms. We reveal the dominance property under the local refinement (LR) operation for the simple CHprogram, as well as the general dominance property under the pseudoLR operation for the monotonicallyconstrained CHprogram and the extendedLR operation for the bounded CHprogram. These properties enable a very efficient polynomialtime algorithm, using different types of LR operations to compute tight lower and upper bounds of the exact solution to any CHprogram. We show that the algorithm is capable of solving many layout optimization problems in deep submicron IC and/or highperformance MCM/PCB designs. In particular, we apply...
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing
"... An interconnect joining a source and a sink is divided into fixedlength uniformwidth wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized ..."
Abstract

Cited by 6 (2 self)
 Add to MetaCart
(Show Context)
An interconnect joining a source and a sink is divided into fixedlength uniformwidth wire segments, and some adjacent segments have buffers in between. The problem we considered is to simultaneously size the buffers and the segments so that the Elmore delay from the source to the sink is minimized. Previously, no polynomial time algorithm for the problem has been reported in literature. In this paper, we present a polynomial time algorithm SBWS for the simultaneous buffer and wire sizing problem. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Also, experimental results show that SBWS is extremely efcient in practice. For example, for an interconnect of 10000 segments and buffers, the CPU time is only 0.127 second.
Wiring layer assignments with consistent stage delays
 PROC. ACM WORKSHOP ON SYSTEMLEVEL INTERCONNECT PREDICTION
, 2000
"... Wire sizing, repeater insertion and repeater sizing are necessary to limit delay in onchip interconnections. When these techniques are applied to nets that are already routed, the results heavily depend on the routing layer chosen for the wire. In this paper, we present alayer assignment method tha ..."
Abstract

Cited by 5 (4 self)
 Add to MetaCart
(Show Context)
Wire sizing, repeater insertion and repeater sizing are necessary to limit delay in onchip interconnections. When these techniques are applied to nets that are already routed, the results heavily depend on the routing layer chosen for the wire. In this paper, we present alayer assignment method that assigns wires to the layer that is best fit. The method is based on a consistent target delay constraint and uses wire sizing and repeater insertion and sizing. It also considers a repeater area constraint and takes the impact of vias into account. A greedy optimization approach is used with the number of layers needed for the wiring as its cost function. Our layer assignment method can be used in conjunction with a priori wirelength estimation models so that it applies both as a guide for the router as well as for placement tools. Our model suggests that vias can severely impact the solution when tight delay constraints are applied, and that this actually sets an upper bound to the number of wires that can be accommodated in any layer stack. Empirical results provide some answers as to the best form of the layer stack. Layer stacks with monotonically increasing wire height on the layers are optimal for tight delay constraints. If longer delays are allowed, the addition of a lowlevel layer on top of the layer stack might be beneficial.
An efficient sequential quadratic programming formulation of optimal wire spacing for crosstalk noise avoidance routing
 in Proceedings of the ISPD
, 1999
"... In this paper we propose a new, and eective, approach to crosstalk noise avoidance routing. In our new approach we attack the crosstalk noise problem immediately following topological routing, which is the point in the routing process that gives the best trade o between the ability to detect cro ..."
Abstract

Cited by 5 (1 self)
 Add to MetaCart
(Show Context)
In this paper we propose a new, and eective, approach to crosstalk noise avoidance routing. In our new approach we attack the crosstalk noise problem immediately following topological routing, which is the point in the routing process that gives the best trade o between the ability to detect crosstalk noise problems and the ability to correct the problems. We formulate the heart of this new approach as a convex, nonlinear, mathematical programming problem which determines an optimal set of wire spacings under crosstalk noise constraints. This new mathematical programming formulation is based on a detailed knowledge of the underlying crosstalk noise mechanisms and accounts for coupling capacitance, interconnect resistance, and aggressor net signal rise time on nets with arbitrarily complex tree topologies. Finally, by slightly restricting this programming problem we formulate it as a linearly constrained, convex, nonlinear, mathematical program which can be quickly and eciently solved using sequential quadratic programming. 1.