Results 1  10
of
19
New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
Abstract

Cited by 34 (1 self)
 Add to MetaCart
(Show Context)
Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.
Gate Sizing for Constrained delay/power/area optimization
 in IEEE Transcation on VLSI Design
, 1997
"... Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to mini ..."
Abstract

Cited by 31 (0 self)
 Add to MetaCart
(Show Context)
Abstract—Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some userdefined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technologydependent optimization has been investigated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on reallife large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I.
Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing
 IEEE Transactions on ComputerAided Design of Integrated Circuits and systems
, 2000
"... Abstract—Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical ..."
Abstract

Cited by 25 (2 self)
 Add to MetaCart
(Show Context)
Abstract—Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicrometer integrated circuits. Currently existing algorithms do not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm which can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement and linear runtime, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1MB memory and 19.4min runtime to achieve the precision of within 1 % error on a SUN Sparc UltraI workstation. Index Terms—Deep submicrometer, gate sizing, interconnect, performance optimization, physical design, routing. I.
A New Statistical Optimization Algorithm for Gate Sizing
"... In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a ..."
Abstract

Cited by 21 (2 self)
 Add to MetaCart
In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a robust linear program that can be solved efficiently. We demonstrate the efficiency and computational tractability of the proposed algorithm on the various ISCAS’85 benchmark circuits. Across the benchmarks, compared to the deterministic approach, the power savings range from 23 − 30 % for the same timing target and the yield level, the average power saving being 28%. The runtime is reasonable, ranging from a few seconds to around 10 mins, and grows linearly.
Power Reduction by Simultaneous Voltage Scaling and Gate Sizing
 in Proc. of ASPDAC’00
, 2000
"... This paper proposes to use voltagescaling (VS) and gatesizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the MaximumWeighted IndependentSet problem. We describe the slack distribution of c ..."
Abstract

Cited by 11 (4 self)
 Add to MetaCart
This paper proposes to use voltagescaling (VS) and gatesizing (GS) simultaneously for reducing power consumption without violating the timing constraints. We present algorithms for simultaneous VS and GS based on the MaximumWeighted IndependentSet problem. We describe the slack distribution of circuit, completeness of gate library and discreteness of supply voltage, and discuss their effects on power optimization. Experimental results show that the average power reduction ranges from 23.3% to 56.9% over all tested circuits. I. INTRODUCTION Because of the increased circuit density and speed, the power dissipation has emerged as an important consideration in circuit design. A lot of efforts on power reduction have been made at various levels of design abstraction (such as system, architectural, logic and layout levels). Considering the fact that the charging/discharging of capacitance is the most significant source of power dissipation in welldesigned CMOS circuits, most research ...
Functional correlation analysis in crosstalk induced critical paths identification
 In Proc. DAC’01
, 2001
"... In deep submicron digital circuits capacitive couplings make delay of a switching signal highly dependent on its neighbors ’ switching times and switching directions. A long path may have a large number of coupling neighbors with difficult to determine interdependencies. Ignoring the mutual relation ..."
Abstract

Cited by 10 (0 self)
 Add to MetaCart
(Show Context)
In deep submicron digital circuits capacitive couplings make delay of a switching signal highly dependent on its neighbors ’ switching times and switching directions. A long path may have a large number of coupling neighbors with difficult to determine interdependencies. Ignoring the mutual relationship among the signals may result in a very pessimistic estimation of circuit delay. In this paper, we apply efficient functional correlation analysis techniques to identify critical paths caused by crosstalk delay effects. We also discuss applications to static timing optimization. Experiments demonstrate efficacy of the proposed technique. 1.
Statistical timing yield optimization by gate sizing
 TCAD
, 2006
"... Abstract—In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework ..."
Abstract

Cited by 6 (4 self)
 Add to MetaCart
(Show Context)
Abstract—In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS’85) and Microelectronics Center of North Carolina (MCNC) benchmarks show absolute timing yield gains of 30 % on the average, over deterministic timing optimization for at most 10 % area penalty. It is further shown that circuits optimized using our metric have larger timing yields than the same optimized using a worst case metric, for isoarea solutions. Finally, we present an insight into statistical properties of gate delays for a commercial 0.13 m technology library which intuitively provides one reason why statistical timing driven optimization does better than deterministic timing driven optimization. Index Terms—Gate sizing, optimization, statistical gate delay modeling, statistical timing analysis, timing yield, variability, VLSI. I.
NoiseConstrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation
 In Proc. of DAC99, Design Automation Conference
, 1999
"... Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicron ICs. Currently existing algorithms can not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but ..."
Abstract

Cited by 5 (3 self)
 Add to MetaCart
Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep submicron ICs. Currently existing algorithms can not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, but also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm that can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement overall and linear runtime per iteration, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1 MB memory and 47 minute runtime to achieve the precision of within 1% error on a SUN UltraSPARCI workstation.
Integrated Resynthesis for Low Power
, 1996
"... Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
Research on synthesis for low power has been done in all three stages of logic synthesis: technology independent optimization, technology mapping, and technology dependent optimization. This paper presents an integrated method, using remapping and technology dependent optimizations, to minimize the power of a mapped circuit under the given delay constraints. It produces 24 % savings in power.
Timing analysis and optimization of a highperformance CMOS processor chipset
 Design, Automation and Test in Europe, Proceedings, IEEE
, 1998
"... We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server Generation 3. After an introduction to the concepts of static timing analysis, we describe the timingmodeling for the gates and interconnects, explain the optimization ..."
Abstract

Cited by 4 (0 self)
 Add to MetaCart
(Show Context)
We describe the timing analysis and optimization methodology used for the chipset inside the IBM S/390 Parallel Enterprise Server Generation 3. After an introduction to the concepts of static timing analysis, we describe the timingmodeling for the gates and interconnects, explain the optimization schemes and present obtained results. 1. Overview After introducing the chipset, the used library and differentiating static timing analysis from simulation in section 2, we go over the basic concepts of static timing analysis in section 3. In section 4, we describe our clocking structure and then, in sections 5 and 6, we explain how circuits and interconnects are modeled for the timingtool. Thus sections 2 through 6 set the stage for the introduction of the optimization scheme, which is presented in sections 7 and 8. In section 9 we share measured results, section 10 gives an outlook on our current work, and the paper wraps up with conclusions in section 11. 2.