Explicitly software managed cache systems are postulated as a solution for power considerations in computing devices. The savings expected in a SoftCache lies in the removal of tag storage, associativity logic, comparators, and other hardware dedicated to memory hierarchies. The penalty lies in high cache-miss cost and additional instructions required to effect a cache model. In this paper, we characterize SoftCaches by placing them in the overall computing landscape, analyzing the energy and space tradeoffs. We present results that indicate a SoftCache saves power and space over hardware caches. Based on the TSMC 0.25 m process from MOSIS, we use schematic and layout representations of hardware and SoftCache models for comparison. Accounting for additional instructions executed and simplification of logic, we examine high SoftCache miss cost in relation to the overall system. For a 256KB "mode" change every 1.45 hours, the SoftCache exhibits 1% application slowdown for energy savings of 30% or more in a low-power device such as the SA-110 microprocessor used in PocketPC platforms.

Currently, there are 23 million Java-enabled handsets with more than 50 different models from 17-plus suppliers. With the growing popularity of such devices, there is a need in the embedded industry for a set of applications for accurate indications of the performance of embedded Java solutions. Towards addressing this problem, we gather a set of 12 Java applications running on PDA and cell phone like devices. We present a machine-independent characterization of the applications, specifically focusing on their memory characteristics. Our focus is motivated by the criticality of memory size constraints and heap footprints on both performance and power budgets.

Power consumption is rapidly becoming the dominant limiting factor for further improvements in computer design. Curiously, this applies both at the “high-end ” of workstations and servers and the “low end ” of handheld devices and embedded computers. At the high-end, the challenge lies in dealing with exponentially growing power densities. At the low-end, there is a demand to make mobile devices more powerful and longer lasting, but battery technology is not improving at the same rate that power consumption is rising. Traditional power-management research is fragmented; techniques are being developed at specific levels, without fully exploring their synergy with other levels. Most software techniques target either operating systems or compilers but do not explore the interaction between the two layers. These techniques also have not fully explored the potential of virtual machines for power management. In contrast, we are developing a system that integrates information from multiple levels of software and hardware, connecting these levels through a communication channel. At the heart of this system are a virtual machine that compiles and dynamically profiles code, and an optimizer that reoptimizes all code, including that of applications and the virtual machine itself. We believe this introspective, holistic approach enables more informed power-management decisions. Information and Computer Science