A highly efficient CMOS line driver with 80-dB linearity for ISDN U-interface applications (1992)

by H Khorramabadi, J Anidjar, T R Peterson
Venue:IEEE J. Solid-State Circuits
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A CMOS Low-Distortion Fully Differential Power Amplifier with Double Nested Miller Compensation

by Sergio Pernici, Gerrnano Nicollini, Rinaldo Castello, Senior Member - IEEE J. Solid-State Circuits , 1993
"... Abstract—A four-stage fully differential power amplifier using a double nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compen ..."
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Abstract—A four-stage fully differential power amplifier using a double nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and THD is-S3 dB for a 6-VP –P differential output signal at 10 kHz and a load of 50 Q. With 8-0 load and for a 10-kHz, 4-VP–P output signal, THD is-68 dB. The chip area is 0.625 mm ’ in a 1.5-~m single-poly, double-metal, n-well CMOS technology I.