Abstract — Three-stage non-blocking switching fabrics are the next step in scaling current crossbar switches to many hundreds or few thousands of ports. Congestion management, however, is the central open problem; without it, performance suffers heavily under real-world traffic patterns. Schedulers for bufferless crossbars perform congestion management but are not scalable to high valencies and to multi-stage fabrics. Distributed scheduling, as used in buffered crossbars, is scalable but has never been scaled beyond crossbar valencies. We combine ideas from central and distributed schedulers, from request-grant protocols and from credit-based flow control, to propose a novel, practical architecture for scheduling in non-blocking buffered switching fabrics. The new architecture relies on multiple, independent, single-resource schedulers, operating in a pipeline. It: (i) isolates well-behaved against congested flows; (ii) provides throughput in excess of 95 % under unbalanced traffic, and delays that successfully compete again output queueing; (iii) provides weighted max-min fairness; (iv) directly operates on variable-size packets or multi-packet segments; (v) resequences cells or segments using very small buffers; and (vi) can be realistically implemented for a 1024×1024 reference fabric made out of 32×32 buffered crossbar switch elements. This paper carefully studies the many intricacies of the problem and the solution, discusses implementation, and provides performance simulation results. 1

Abstract—The crossbar fabric is widely used as the interconnect of high-performance packet switches due to its low cost and scalability. There are two main variants of the crossbar fabric: unbuffered and internally buffered. On one hand, unbuffered crossbar fabric switches exhibit the advantage of using no internal buffers. However, they require a complex scheduler to solve input and output ports contention. Internally, buffered crossbar fabric switches, on the other hand, overcome the scheduling complexity by means of distributed schedulers. However, they require expensive internal buffers—one per crosspoint. In this paper, we propose a novel architecture, namely, the Partially Buffered Crossbar (PBC) switching architecture, where a small number of separate internal buffers are maintained per output. Our goal is to design a PBC switch having the performance of buffered crossbars and a cost comparable to that of unbuffered crossbars. We propose a class of round robin scheduling algorithms for the PBC architecture. Simulations results show that using as few as eight buffers per fabric column and irrespective of the number N of input ports of the switch, we can achieve similar performance to buffered crossbars that use N buffers per fabric output. Index Terms—Crossbar fabrics, partially buffered crossbars, scheduling. Ç

Abstract — We consider a switch with small output queues, shared among the input VOQ linecards. This has been shown to be a useful abstract model for realistic buffered switching fabrics. Cells are being scheduled by a central control unit, comprising independent, single resource schedulers, working in pipeline. This unit allocates output buffer credits to the requesting VOQs. We show how particular unbalanced transient VOQ states, produced by bursty traffic, affect credit reservations: when some input temporarily constitutes a bottleneck, too many credits may get reserved for it at once, leading to poor overall performance. We propose a threshold grant throttling method to control these credit accumulations. Then, we show how, under such grant throttling, typical round-robin credit schedulers can get synchronized, thus deteriorating performance. To avoid scheduler synchronization, we propose modified round-robin disciplines. Simulations under both smooth and bursty traffic demonstrate the effectiveness of the combined method: using only a 12-cell buffers per-output, for any switch size, N, and independently of the number of cells in transit between the linecards and the fabric, the performance achieved is very close to that of pure output queueing. We also discuss the operation of the independent input and output schedulers inside the control unit, their relation with PIM-like schedulers, and their relation with buffered crossbar schedulers. 1