### JANUARY 1982

"... ged SAW correlation, that require no adjustment make real-time convolution, correlation, and dispersive filtering less difficult. ..."

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ged SAW correlation, that require no adjustment make real-time convolution, correlation, and dispersive filtering less difficult.

### 1250 A Concurrent IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL. 7. NO 12. DECEMBER 1988 Testing Technique for Digital Circuits

"... Abstract-In this paper, we present a method of testing digital cir-cuits during normal operation. The resources used to perform on-line testing are those which are inserted to alleviate the off-line testing problem. The off-line testing resources are modified such that during system operation they c ..."

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Abstract-In this paper, we present a method of testing digital cir-cuits during normal operation. The resources used to perform on-line testing are those which are inserted to alleviate the off-line testing problem. The off-line testing resources are modified such that during system operation they can also observe the normal inputs and outputs of a combinational circuit under test. The normal inputs to the circuit under test are compared with test vectors in its test set. When a normal input matches a test vector, the circuit output for such an input is typ-ically compressed into a developing signature. When all of the test vec-tors in the test set have appeared as normal inputs, the signature is read and verified. With this method, the length of time required for all of the test vec-tors to appear, possibly in some order, among the normal inputs to the circuit under test is of considerable importance. We refer to this as the test latency and give analytical methods for its computation with ver-ification by simulation. We also describe a hardware structure for im-plementing the concurrent test method and identify a number of ap-proaches for reducing test latency. Zndex Terms-Concurrent testing, test latency, built-in-self-test, VLSI testing, testable design. I.

### 9 1996 Kluwer Academic Publishers. Manufactured in The Netherlands. Balance Testing and Balance-Testable Design of Logic Circuits*

, 1994

"... Abstract. We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zero ..."

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Abstract. We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100 % either by adding tests or applying DFBT.

### Aliasing Probability Calculations in Testing Sequential Circuits

"... This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a give ..."

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This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a given finite state machine (FSM) and the final FSM output is used to verify the functionality of the FSM. We also explore how the aliasing probability is affected when the output mapping (from the set of states to the set of outputs) of the FSM under test changes.

### Development of State Model Theory for External Exclusive NOR Type LFSR Structures

"... Abstract—Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed. Through this tool a systematic procedure is devised for computing pseudo-random binary sequences from such structures. Keywords—LFSR, external exclusive NOR type, r ..."

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Abstract—Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed. Through this tool a systematic procedure is devised for computing pseudo-random binary sequences from such structures. Keywords—LFSR, external exclusive NOR type, recursive binary sequence, initial state- next state, state transition matrix. I.

### Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems

"... The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total developm ..."

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The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques.

### References

"... We study global routing of multiterminal nets. We propose a new global router; each step consists of finding a tree, called Steiner min-max tree, that is, a Steiner tree with maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent int ..."

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We study global routing of multiterminal nets. We propose a new global router; each step consists of finding a tree, called Steiner min-max tree, that is, a Steiner tree with maximum-weight edge minimized (real vertices represent channels containing terminals of a net, Steiner vertices represent intermediate channels, and weights correspond to densities). We propose an effient algorithm for obtaining a Steiner min-max tree, in a weighted graph. Experimental results on difficult examples, on randomly generated data, on master slice chips, and on benchmark examples from Physical Design Workshop are

### TABLE I1 COVERAGE OBTAINED FOR DETERMINST~C TEST SEQUENCES Circuit Test Patterns C,,,,, cc,,, I Cex,,,- cm I

, 1000

"... Number of Gates Normalized CPU time as a function of the number of pates. The data have been normalized with respect to the case of the largckst circuit (C7552). Symbols 0 and V denote the fault free and heuristic simulation time, respectively. ..."

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Number of Gates Normalized CPU time as a function of the number of pates. The data have been normalized with respect to the case of the largckst circuit (C7552). Symbols 0 and V denote the fault free and heuristic simulation time, respectively.

### On Analog Signature Analysis Franc Novak

"... We formalize the problem of analog data compression and analyze the existence of a polynomial data compression function. Under relaxed conditions we explore the existence of a solution employing digital signature analysis in the analog domain. 1 ..."

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We formalize the problem of analog data compression and analyze the existence of a polynomial data compression function. Under relaxed conditions we explore the existence of a solution employing digital signature analysis in the analog domain. 1