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12
RandomPattern Coverage Enhancement and Diagnosis for LSSD Logic SelfTest
 IBM Journal of Research and Development
, 1983
"... Embedded linear feedback shift registers can be used for logic component selftest. The issue of test coverage is addressed by circuit modification, where necessary, of randompatternresistant fault nodes. Also given is a procedure that supports netlevel diagnosis for structured logic in the prese ..."
Abstract

Cited by 62 (1 self)
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Embedded linear feedback shift registers can be used for logic component selftest. The issue of test coverage is addressed by circuit modification, where necessary, of randompatternresistant fault nodes. Also given is a procedure that supports netlevel diagnosis for structured logic in the presence of random testpattern generation and signature analysis.
Test Time Optimization in . . .
, 2010
"... As circuit sizes increase with scale down in technology, the time required to test the circuits also increases. Expensive automatic test equipment (ATE) is used to test these circuits and the cost of testing becomes a significant fraction of the total cost of the chip. Testing cost of a chip is dire ..."
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Cited by 7 (4 self)
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As circuit sizes increase with scale down in technology, the time required to test the circuits also increases. Expensive automatic test equipment (ATE) is used to test these circuits and the cost of testing becomes a significant fraction of the total cost of the chip. Testing cost of a chip is directly related to the time its testing takes. However, test time cannot be reduced by simply applying the tests at a faster speed because if the test clock frequency is increased, the power consumed during test increases. If this power were to exceed the power consumption the chip can withstand, the circuit might perform slower or might malfunction [52]. This research aims at reducing the time required for test without increasing the power dissipated during test. Full scan design is a popular design for testability (DFT) method [11] in which the flipflops of the circuit are chained together to function as a shift register during test. Test vectors are scanned in and the responses are scanned out bit by bit. The power consumption during test can exceed the power consumption in the functional mode
Xcodes: Theory and applications of unknowable inputs
, 2003
"... This paper studies the properties of a new class of codes introduced recently (and currently being ..."
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Cited by 4 (0 self)
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This paper studies the properties of a new class of codes introduced recently (and currently being
Development of State Model Theory for External Exclusive NOR Type LFSR Structures
"... Abstract—Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed. Through this tool a systematic procedure is devised for computing pseudorandom binary sequences from such structures. Keywords—LFSR, external exclusive NOR type, r ..."
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Cited by 3 (2 self)
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Abstract—Using state space technique and GF(2) theory, a simulation model for external exclusive NOR type LFSR structures is developed. Through this tool a systematic procedure is devised for computing pseudorandom binary sequences from such structures. Keywords—LFSR, external exclusive NOR type, recursive binary sequence, initial state next state, state transition matrix. I.
Spectral Analysis for Statistical Response Compaction During BuiltIn SelfTesting
 in Proc. of the International Test Conf
, 2004
"... Spectral generation of patterns, to excite the natural frequencies of a digital circuit, is highly effective in testing sequential circuits. We have created a hardware embodiment of the spectral testpattern generator for builtin selftest (BIST). We present five new spectral response compactors SR ..."
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Cited by 2 (0 self)
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Spectral generation of patterns, to excite the natural frequencies of a digital circuit, is highly effective in testing sequential circuits. We have created a hardware embodiment of the spectral testpattern generator for builtin selftest (BIST). We present five new spectral response compactors SRC15 for BIST. Each analyzes the spectral content of circuit output responses, and accumulates their spectrum in one or more counters. The method has astonishing results. SRC1 never aliased for any faults in the ISCAS ’89 benchmarks. SRC2, a lowoverhead version of SRC1, aliased slightly more than the multipleinput signature register (MISR), but used less hardware than the MISR. This new spectral BIST system has a 91.26 % shorter test sequence than for a conventional LFSR pattern generator and MISR system, with at least 8.42 % higher fault coverage. The benefits of this are drastically shorter test sequences, the elimination of scanshifting sequences, much lower test power dissipation, and higher fault coverage. 1
A Simulation Experiment on a BuiltIn Self Test Equipped with Pseudorandom Test Pattern Generator and MultiInput Shift Register (MISR
 International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.4
, 2010
"... This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (MultiInput Shift Register), used in an LFSR based digital circuit testing technique. The investigation is carriedout through an ..."
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Cited by 2 (1 self)
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This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (MultiInput Shift Register), used in an LFSR based digital circuit testing technique. The investigation is carriedout through an extensive simulation study of the effectiveness of the LFSR based digital circuit testing technique. The results of the study show that when the identical characteristic polynomials of order n are used in both pseudorandom testpattern generator, as well as in MultiInput Shift Register (MISR) signature analyzer (parallel type) then the probability of aliasing errors remains unchanged due to the changes in the initial loadings of the pseudorandom testpattern generator.
Aliasing Probability Calculations in Testing Sequential Circuits
"... This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a give ..."
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This paper focuses on testing sequential circuits using a simple form of signature analysis as a compaction technique. More specifically, the paper describes a systematic methodology for calculating the probability of aliasing when a randomly generated test input vector sequence is applied to a given finite state machine (FSM) and the final FSM output is used to verify the functionality of the FSM. We also explore how the aliasing probability is affected when the output mapping (from the set of states to the set of outputs) of the FSM under test changes.
On Analog Signature Analysis Franc Novak
"... We formalize the problem of analog data compression and analyze the existence of a polynomial data compression function. Under relaxed conditions we explore the existence of a solution employing digital signature analysis in the analog domain. 1 ..."
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We formalize the problem of analog data compression and analyze the existence of a polynomial data compression function. Under relaxed conditions we explore the existence of a solution employing digital signature analysis in the analog domain. 1
JANUARY 1982
"... ged SAW correlation, that require no adjustment make realtime convolution, correlation, and dispersive filtering less difficult. ..."
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ged SAW correlation, that require no adjustment make realtime convolution, correlation, and dispersive filtering less difficult.
HighPerformance Computing with Dual ALU Architecture and ECL Logic, by Frederic
, 1982
"... the one million instructions per second class. ..."