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11
CouplingDriven Signal Encoding Scheme for LowPower Interface Design
, 2000
"... Coupling effects between onchip interconnects must be addressed in ultra deep submicron VLSI and systemonachip (SoC) designs. A new lowpower bus encoding scheme is proposed to minimize coupled switchings which dominate the onchip bus power consumption. The couplingdriven bus invert method use ..."
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Cited by 34 (3 self)
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Coupling effects between onchip interconnects must be addressed in ultra deep submicron VLSI and systemonachip (SoC) designs. A new lowpower bus encoding scheme is proposed to minimize coupled switchings which dominate the onchip bus power consumption. The couplingdriven bus invert method use slim encoder and decoder architecture to minimize the hardware overhead. Experimental results indicate that our encoding methods save effective switchings as much as 30% in an 8bit bus with onecycle redundancy. 1 Introduction Increased coupling effect between interconnects in ultra deep submicron technology not only aggravates the powerdelay metrics but also deteriorates the signal integrity due to capacitive and inductive crosstalk noises. Conventional approaches to interconnect synthesis aim at optimal interconnect structures in terms of interconnect topology, wire width and spacing, and buffer location and sizes [3]. In this paper, we study a signal encoding scheme to minimize coupli...
Odd/even bus invert with twophase transfer for buses with coupling
 International Symposium on Low Power Electronics and Design 2002
, 2002
"... The coupling capacitances between onchip bus lines become dominant in deepsubmicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are ..."
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Cited by 25 (0 self)
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The coupling capacitances between onchip bus lines become dominant in deepsubmicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are needed for deepsubmicron buses. One such coding technique uses the simple observation that coupling capacitances are always charged and discharged by activity on neighboring bus lines, where one line has an odd number and the other has an even number (if bus lines are numbered “inorder”). We thus propose to reduce the coupling activity by independently controlling the odd and even bus lines with two separate lines, the Odd Invert, and Even Invert line, respectively. We obtain significant reductions in power simply by comparing the coupling activity for the four possible cases of the Odd and Even Invert lines (00, 01, 10, 11), and then choosing the value with the smallest coupling activity to transmit on the bus. Even after encoding, the coupling activity for a pair of bus lines is still strongly dependent on the data. In particular the toggling sequences 01→10 and 10→01 result in 4 times more coupling energy dissipation than other coupling events. We thus propose a targeted TwoPhase transfer in order to reduce total power only on the pairs of lines that carry such toggling events.
Bus Energy Reduction by Transition Pattern Coding Using a Detailed Deep Submicrometer Bus Model
, 2003
"... A datadistribution and busstructure aware methodology for the design of coding schemes for lowpower onchip and interchip communication is presented. A general class of coding schemes for low power, termed transition pattern coding schemes, is introduced. The energy behavior of the schemes is mat ..."
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Cited by 12 (0 self)
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A datadistribution and busstructure aware methodology for the design of coding schemes for lowpower onchip and interchip communication is presented. A general class of coding schemes for low power, termed transition pattern coding schemes, is introduced. The energy behavior of the schemes is mathematically analyzed in detail. Two algorithms are proposed for deriving such efficient coding schemes, which are optimized for desired bus structures and data distributions. Bus partitioning is proposed and mathematically analyzed as a way to reduce the complexity of the encoder/decoder.
Theoretical analysis of businvert coding
 IEEE Trans. VLSI Syst
, 2002
"... AbsfructExact formulas to compute the switching activities of the invert line and each bus line for both even and odd bus widths are presented. This enables us to understand the finite and asymptotic behaviors of the businvert coding process. It is found that the previous published theoretical res ..."
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Cited by 4 (0 self)
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AbsfructExact formulas to compute the switching activities of the invert line and each bus line for both even and odd bus widths are presented. This enables us to understand the finite and asymptotic behaviors of the businvert coding process. It is found that the previous published theoretical results form only a subset of our contributions. I.
BusSwitch Coding for Reducing Power Dissipation in OffChip
, 2004
"... We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving offchip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reodering of bus line positions,in order to minimize the toggli ..."
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Cited by 2 (0 self)
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We present a novel coding scheme for reducing bus power dissipation. The presented approach is well suited to driving offchip buses, where the line capacitance is a dominant factor. A distinctive feature of the technique is the dynamic reodering of bus line positions,in order to minimize the toggling activity on physical bus wires. The effectiveness of the approach is demonstrated through cycleaccurate simulation of industrial benchmarks in conjunction with postlayout evaluation of speed,po wer and area overhead.
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"... The coupling capacitances between onchip bus lines become dominant in deepsubmicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are ..."
Abstract
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The coupling capacitances between onchip bus lines become dominant in deepsubmicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are needed for deepsubmicron buses. One such coding technique uses the simple observation that coupling capacitances are always charged and discharged by activity on neighboring bus lines, where one line has an odd number and the other has an even number (if bus lines are numbered “inorder”). We thus propose to reduce the coupling activity by independently controlling the odd and even bus lines with two separate lines, the Odd Invert, and Even Invert line, respectively. We obtain significant reductions in power simply by comparing the coupling activity for the four possible cases of the Odd and Even Invert lines (00, 01, 10, 11), and then choosing the value with the smallest coupling activity to transmit on the bus. Even after encoding, the coupling activity for a pair of bus lines is still strongly dependent on the data. In particular the toggling sequences 01→10 and 10→01 result in 4 times more coupling energy dissipation than other coupling events. We thus propose a targeted TwoPhase transfer in order to reduce total power only on the pairs of lines that carry such toggling events.
Energy Reduction in VLSI Computation Modules: An InformationTheoretic Approach
 IEEE TRANSACTIONS ON INFORMATION THEORY
, 2003
"... We consider the problem of reduction of computation cost by introducing redundancy in the number of ports as well as in the input and output sequences of computation modules. Using our formulation, the classical "communication scenario" is the case when a computation module has to recomput ..."
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We consider the problem of reduction of computation cost by introducing redundancy in the number of ports as well as in the input and output sequences of computation modules. Using our formulation, the classical "communication scenario" is the case when a computation module has to recompute the input sequence at a different location or time with high fidelity and low biterror rates. We then consider communication with different computational cost objective than that given by biterror rate. An example is communication over deep submicrometer verylarge scale integration (VLSI) buses where the expected energy consumption per communicated information bit is the cost of computation. We treat this scenario using tools from information theory and establish fundamental bounds on the achievable expected energy consumption per bit in deep submicrometer VLSI buses as a function of their utilization. Some of our results also shed light on coding schemes that achieve these bounds. We then prove that the best tradeoff between the expected energy consumption per bit and bus utilization can be achieved using codes constructed from typical sequences of Markov stationary ergodic processes. We use this observation to give a closedform expression for the best tradeoff between the expected energy consumption per bit and the utilization of the bus. This expression, in principle, can be computed using standard numerical methods. The methodology developed here naturally extends to more general computation scenarios.
Switching Activity Minimization by Efficient Instruction Set Architecture Design
"... Power consumption can be greatly minimized by reducing the bus signal transition activity (also called switching activity) in the control and data path circuit. Switching activity occurs due to the switching between two instructions (of the embedded software) on successive clock cycles. Our belief i ..."
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Power consumption can be greatly minimized by reducing the bus signal transition activity (also called switching activity) in the control and data path circuit. Switching activity occurs due to the switching between two instructions (of the embedded software) on successive clock cycles. Our belief is that the binary encoding of instructions (machine code) plays a significant role in determining the amount of switching in a circuit. Thus, our aim is to realise a machine encoding of instructions of an ASIP such that for a given data path, it will minimize the average switching activity in the control path circuit of the ASIP and hence the total switching activity in the ASIP. Given the applicationdomain of the ASIP, we have used information theoretic techniques to arrive at an encoding of the opcode that minimizes redundancy and also the switching activity. We have compared our encoding of instruction opcodes with those obtained by other encoding techniques using a switching activity estimator designed by us. 1.
D83 Acknowledgement
"... This dissertation was written during my employment time as a research associate at ..."
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This dissertation was written during my employment time as a research associate at