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A Separator Theorem for Planar Graphs f
, 1977
"... Let G be any nvertex planar graph. We prove that the vertices of G can be partitioned into three sets A, B, C such that no edge joins a vertex in A with a vertex in B, neither A nor B contains more than 2n/3 vertices, and C contains no more than 2& & vertices. We exhibit an algorithm which finds su ..."
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Cited by 397 (1 self)
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Let G be any nvertex planar graph. We prove that the vertices of G can be partitioned into three sets A, B, C such that no edge joins a vertex in A with a vertex in B, neither A nor B contains more than 2n/3 vertices, and C contains no more than 2& & vertices. We exhibit an algorithm which finds such a partition A, B, C in O(n) time.
Efficient Extraction of Multiple Kuratowski Subdivisions (TR)
, 2007
"... Abstract. A graph is planar if and only if it does not contain a Kuratowski subdivision. Hence such a subdivision can be used as a witness for nonplanarity. Modern planarity testing algorithms allow to extract a single such witness in linear time. We present the first linear time algorithm which is ..."
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Cited by 2 (1 self)
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Abstract. A graph is planar if and only if it does not contain a Kuratowski subdivision. Hence such a subdivision can be used as a witness for nonplanarity. Modern planarity testing algorithms allow to extract a single such witness in linear time. We present the first linear time algorithm which is able to extract multiple Kuratowski subdivisions at once. This is of particular interest for, e.g., BranchandCut algorithms which require multiple such subdivisions to generate cut constraints. The algorithm is not only described theoretically, but we also present an experimental study of its implementation. 1
TwoLayer Wiring With Pin Preassignments is Easier If the Power Supply Nets Are Already Generated
, 1994
"... We examine the constrained via minimization problem with pin preassignments (CVMPP) which arises in connection with hierarchical physical synthesis. Let A be a circuit composed of subcircuits B, C, D, . . .. Assume that the placement and routing phase together with the 2layer wiring of the subcircu ..."
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We examine the constrained via minimization problem with pin preassignments (CVMPP) which arises in connection with hierarchical physical synthesis. Let A be a circuit composed of subcircuits B, C, D, . . .. Assume that the placement and routing phase together with the 2layer wiring of the subcircuits, and the placement and routing phase without the 2layer wiring of A are completed. CVMPP is the problem of finding a 2layer wiring ffi A of A which is induced by the 2layer wirings of the subcircuits and which contains a minimal amount of vias on this condition. First, we show that CVMPP is NPhard. In the case that the wiring of the power supply nets has already been generated we present a polynomial time algorithm solving CVMPP. 1 Introduction Today's integrated circuits have up to several hundred thousand transistors. Processing such designs in a naive manner requires very large internal representations with some millions of data so that even linear space (time) optimization algo...